Flash memory having transistor redundancy

Details Flash memory having transistor redundancy Flash memory having transistor redundancy

1995-02-23

1996-09-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36518509, 36518529, G11C 1140

Patent

active

055597424

ABSTRACT:
A flash memory array comprises a primary row line and a redundant row line each having memory cells therealong. A method of accessing the flash memory array comprises preprogramming all said memory cells. Next, all memory cells are erased simultaneously. Subsequently, all memory cells along the primary row line are programmed and the cells along the redundant row line are selectively programmed. The primary row line is bypassed during any read cycle.

REFERENCES:
patent: 5058071 (1991-10-01), Kohda et al.
patent: 5233559 (1993-08-01), Brennan, Jr.
patent: 5329488 (1994-07-01), Hashimoto
patent: 5388076 (1995-02-01), Ihara

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