Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2003-03-17
2004-10-19
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S239000, C257S261000, C257S315000, C257S316000, C257S324000, C438S201000, C438S211000, C438S257000, C438S593000
Reexamination Certificate
active
06806517
ABSTRACT:
DESCRIPTION OF THE BACKGROUND ART
In general, semiconductor memory devices for storing data are divided into volatile memory devices, which are likely to lose their data when the power supply is interrupted, and nonvolatile memory devices, which can retain their data even when the power supply is interrupted. Compared to other nonvolatile memory technologies, e.g., disk drives, nonvolatile semiconductor memories are relatively small. Accordingly, nonvolatile memory devices have been widely employed in mobile telecommunications systems, memory cards, etc.
Recently, nonvolatile memory devices having silicon-oxide-nitride-oxide-silicon (SONOS) structures, e.g., SONOS-type nonvolatile memory devices, have been proposed. The SONOS-type nonvolatile memory devices have thin cells which are simple to manufacture and can be easily incorporated, e.g., into a peripheral region and/or a logic region of an integrated circuit.
A SONOS-type nonvolatile semiconductor memory device according to the Background Art will be described with reference to FIG.
1
. The SONOS-type nonvolatile semiconductor memory device
10
includes: a silicon substrate
5
having doped source and drain regions
5
; a tunnel oxide layer
1
; a nitride layer
2
on the tunnel oxide layer
1
; a top oxide layer
3
on the nitride layer
2
; and a polycrystalline silicon (polysilicon) gate layer
4
on the top oxide layer
3
. Together the layers
1
,
2
and
3
define an oxide-nitride-oxide (ONO) structure
1
/
2
/
3
.
In operation, electrons or holes are injected into the tunnel oxide layer
1
from the inversion region induced between the source
5
and drain
5
. The nitride layer
2
is a charge trapping layer that traps electrons or holes that penetrate through the tunnel oxide layer
1
. The top oxide layer
3
is provided to prevent any electrons or holes that escape the trapping layer
2
from reaching the polycrystalline silicon layer
4
during write or erase operations. The structure
10
can be described as a stacked SONOS-type cell.
When the gate electrode
4
is positively charged, electrons from the semiconductor substrate
6
become trapped in a region
7
of the nitride layer
2
. Conversely, when the gate electrode
4
is negatively charged, holes from the semiconductor substrate
6
become trapped in the region
7
. The depiction of the region
7
in
FIG. 1
is asymmetric with respect to a vertical center line (not depicted) of the SONOS-type semiconductor memory device
10
.
FIG. 1
assumes a situation in which the drain corresponds to the region
5
at the right side of
FIG. 1
while the source corresponds to the region
5
at the left side of
FIG. 1
, with the drain also assumed to be biased at a higher voltage than the source. Accordingly, electrons/holes accumulate near the higher-biased drain.
The electrons or the holes trapped in the region
7
can change the threshold voltage of the entire nonvolatile semiconductor memory device. When the gate threshold voltage reaches a predetermined level, i.e., when the current of a channel is reduced to a sufficiently low level, the programming process stops. The threshold voltage Vth is set to a value at which a bit ‘0’ can be distinguished consistently from a bit ‘1’ for data that has been retained a predetermined amount of time (rephrasing, Vth is set to a value at which a predetermined amount of data retention time can be achieved consistently).
Since an ONO structure (
1
/
2
/
3
) exists above the entire channel region, the stacked SONOS-type cell
10
has a high initial threshold voltage Vth (and corresponding high power consumption) and a high program current. Because of the high threshold voltage Vth, it is difficult to merge (or integrate) on one chip both the stacked SONOS-type cell and general logic product having a low initial threshold voltage Vth.
In addition, in the stacked SONOS-type cell
10
, electrons trapped in the nitride layer
2
can move laterally along the nitride layer, and thus an erase operation may not be completely performed. If programming operations and erase operations are repetitively performed, the initial threshold voltage Vth can increase, which can reduce the data retention time.
To address such problems, SONOS-type devices having various structures have been developed in the Background Art, e.g., the local SONOS-type cell
20
shown in FIG.
2
. The SONOS-type cell
20
includes: a silicon substrate
26
having doped source and drain regions
25
; a tunnel oxide layer
21
on the substrate
26
; nitride layer segments
28
and
29
on the tunnel oxide layer
21
; a dielectric layer
27
on the tunnel oxide layer
21
; a top oxide layer
23
on the nitride layer segment
28
, the dielectric layer
27
and the nitride layer segment
29
; and a polycrystalline silicon gate layer
4
on the top oxide layer
23
.
In contrast to
FIG. 1
, where the tunnel oxide layer
2
entirely covers the channel region between the source and drain regions
5
the nitride layer (not depicted, but from which the nitride layer segments
28
and
29
were formed) has had a center section removed, resulting in the nitride layer segments
8
and
9
. By separating the nitride layer segments
28
and
29
(and filling the resulting gap with the dielectric layer
27
), trapped electrons that would otherwise be able to migrate laterally along the nitride layer
2
of
FIG. 1
are prevented from moving from the nitride layer segment
28
to the nitride layer segment
29
and vice versa. This improves the data retention time of the SONOS-type cell
20
relative to the SONOS-type cell
10
. The separated ONO structures
21
/(
28
or
29
)/
23
are the reason for describing the SONOS-type cell
20
as a local SONOS-type cell. However, because a thick dielectric structure (layers
27
and
23
) exists above the entire channel region (especially in the portion over which lies the layer
27
), the local SONOS-type cell
20
still has a high initial threshold voltage Vth.
FIG. 3
is a diagram showing another local SONOS-type cell
30
according to Background Art. The local SONOS-type cell
30
includes: a silicon substrate
26
having doped source and drain regions
25
; an oxide layer
32
on the substrate
26
, the oxide layer
32
having branches
34
and
38
; nitride layer segments
36
formed between pairs of oxide layer branches
34
and
38
, respectively; and a polycrystalline silicon gate layer
40
. Each nitride layer segment
36
sandwiched between oxide branches
34
and
38
defines an ONO structure
34
/
36
/
38
. The portion of the oxide layer
32
between the ONO structures is significantly thinner than the corresponding dielectric structure
27
/
23
in the local SONOS-type cell
20
of
FIG. 2
, which can improve (namely, lower) the threshold voltage Vth.
The operating characteristics of the local SONOS-type cell
30
can vary considerably depending on the length (L) of the overlap between the ONO structure
34
/
36
/
38
and the gate layer
40
, where L is substantially the same as the length of the nitride layer segment
36
. Accordingly, it is important to minimize variation in the length of the overlap between the ONO structures
34
/
36
/
38
and the gate
40
.
Photolithography is used to define the length of the ONO structures
34
/
36
/
38
in FIG.
3
. During the photography portion of the photolithography process, misalignment can occur, resulting in significant overlap variation.
To help depict the misalignment problem,
FIGS. 4A and 4B
are provided.
FIG. 4A
is a cross-section (of an intermediate structure produced at one stage in the manufacture of the SONOS-type cell
30
in
FIG. 3
) showing substantial alignment.
FIG. 4B
is a similar cross-section showing significant misalignment. To help convey the relationship between FIG.
3
and
FIGS. 4A and 4B
, regarding the arrangement of lays in
FIG. 3
underneath the bracket
42
, a corresponding arrangement of layers in
FIG. 4
is located underneath bracket
442
.
The intermediate structure
400
in
FIG. 4A
includes: a silicon semiconductor substrate
402
; an O
Bae Geum-Jong
Kim Ki Chul
Kim Sang Su
Lee Nae-In
Rhee Hwa Sung
Harness Dickey
Huynh Andy
Nelms David
Samsung Electronics Co,. Ltd.
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