Flash memory having adaptive sensing and method

Details Flash memory having adaptive sensing and method Flash memory having adaptive sensing and method

1994-12-06

1996-07-16

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

36518533, 36518529, G11C 1300

Patent

active

055373585

ABSTRACT:
A flash memory system including an array of flash memory cells and at least one programmed reference cell and at least one erased reference cell disposed in a common integrated circuit. Memory array read operations are carried out by reading the two reference cells and the target cell of the memory array. The two reference cells produce a programmed reference output and an erased reference output which are averaged to provide a reference value to be compared with the read output of the target cell. In that the reference value is derived by on-chip programmed and erased cells, the reference value will automatically adapt to changes in the fabrication process, temperature, operating voltages and the like. Preferably, the reference cell outputs are also utilized to adaptively control the programming and erasing of the memory array cells so as to control the erased and programmed threshold voltages of the array cells.

REFERENCES:
patent: 5400287 (1995-03-01), Fuchigami
patent: 5414664 (1995-03-01), Lin et al.

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