Flash memory for reducing peak current

Details Flash memory for reducing peak current Flash memory for reducing peak current

2005-09-27

2005-09-27

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280, C365S185330

Reexamination Certificate

active

06950346

ABSTRACT:
In a flash memory, non-selected bit lines prohibited from being programmed are first charged to a predetermined level and then a pumping voltage is generated, the precharging operation to all the bit lines is completed so that a peak current due to a voltage charging concentration is suppressed or decentralized, the memory cell array is divided into two or more portions, and the bit lines are precharged; the flash memory includes a memory cell array having pages that each include memory cells and bit lines and source lines, a first circuit for charging non-selected bit lines among the bit lines to a first voltage level at a first time, a second circuit for generating a pumping voltage higher than a power supply voltage at a second time, and a third circuit for charging the bit lines to a second voltage level at a third time.

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patent: 1 235 230 (2002-08-01), None

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