Flash memory erase verification systems and methods

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185050, C365S185330

Reexamination Certificate

active

11201620

ABSTRACT:
Systems and methods are disclosed herein to provide improved verification of flash memory erasure. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an array of flash memory cells. A plurality of sense amplifiers are also provided wherein each sense amplifier is associated with a plurality of the flash memory cells and adapted to detect a state of one of the associated flash memory cells selected from the plurality of flash memory cells. A first logic circuit is also provided to receive the states of the selected flash memory cells from the sense amplifiers and perform a first logic operation at approximately the same time on the states to verify that all states of the selected flash memory cells correspond to an erased state.

REFERENCES:
patent: 5239505 (1993-08-01), Fazio et al.
patent: 5526309 (1996-06-01), Jinbo
patent: 5831905 (1998-11-01), Hirano
patent: 6477090 (2002-11-01), Yamaki et al.
patent: 6657900 (2003-12-01), Roohparvar
patent: 6807096 (2004-10-01), Toda
MICRON, Flash Memory, 4Mb Smart 3 Boot Block Flash Memory, Rev. 2, Pub. Mar. 1, 2001, Micron Technology, Inc., pp. 1-30.

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