Flash memory devices with trimmed analog voltages

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S185180, C365S185210

Reexamination Certificate

active

11332567

ABSTRACT:
A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

REFERENCES:
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5675546 (1997-10-01), Leung
patent: 5936906 (1999-08-01), Tsen
patent: 6091631 (2000-07-01), Kucera et al.
patent: 6184726 (2001-02-01), Haeberli et al.
patent: 6201734 (2001-03-01), Sansbury et al.
patent: 6301151 (2001-10-01), Engh et al.
patent: 6370061 (2002-04-01), Yachareni et al.
patent: 6490201 (2002-12-01), Sakamoto
patent: 6747892 (2004-06-01), Khalid
patent: 7020037 (2006-03-01), Anzai et al.
patent: 2002/0085436 (2002-07-01), Chang
patent: 2003/0002334 (2003-01-01), Ho Chang
patent: 2005/0213378 (2005-09-01), Chang
Jung et al., “A 117-mm2 3.3-V Only 128 Mb Multilevel NAND Flash Memory for Mass Storage Applications”, J. Solid State Circ., vol. 31, No. 11 (1996), pp. 1757-1583.
Takeuchi et al., “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories”, J. Solid State Circ., vol. 33, No. 8 (1998), pp. 1228-1238.
Cho et al., “A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes”, J. Solid State Circ., vol. 36, No. 11 (2001), pp. 1700-1706.
Elmhurst et al., “A 1.8-V 128-Mb 125-MHz Multilevel Cell Flash Memory With Flexible Read While Write”, J. Solid State Circ., vol. 38, No. 11 (2003), pp. 1929-1933.

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