Flash memory devices with oxynitride dielectric as the...

Details Flash memory devices with oxynitride dielectric as the... Flash memory devices with oxynitride dielectric as the...

2003-01-14

2004-09-28

Wilson, Allan R. (Department: 2815)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S769000

Reexamination Certificate

active

06797650

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and more particularly to flash memory.
BACKGROUND OF THE INVENTION
There has long been a demand for small, portable personal devices. These devices include cellular phones, personal computing equipment, and personal sound systems, which are sought in continuously smaller sizes and with continuously lower power requirements. At the same time that smaller and more portable devices are sought, computational power and on-chip memory requirements are increasing. In light of these requirements, there has been a long-felt need for computational devices that have substantial memory and logic functions integrated within individual semiconductor chips. Preferably, the memory is configured such that if power is interrupted, as when a battery fails, the contents of the memory are retained. Memory that retains its content without a continuous supply of power is called non-volatile memory. Non-volatile memory types include, for example, electrically erasable, programmable read only memory (EEPPROM) and flash EEPROM. The term “flash” refers to the ability of the memory to be erased in blocks. Flash memory devices store electrical charge, representing data, in transistors having either a floating gate or a charge-trapping dielectric.
Conventional flash memory uses a floating gate. A floating gate memory cell characteristically includes a vertical stack of a tunnel oxide, a first polysilicon layer (the floating gate), an ONO tri-layer (silicon oxide, silicon nitride, silicon oxide) interlevel dielectric, and a second polysilicon layer (control gate) over the interlevel dielectric. Thus, the conductive floating gate is sandwiched between two dielectrics.
A floating gate memory cell can be programmed by inducing hot electron injection from a portion of the substrate, such as the channel near a drain region, to the floating gate. Typically, a source region and a bulk portion of the substrate are grounded while a relatively high positive voltage is applied to the control gate. A moderate positive voltage is applied to the drain region causing electrons to flow from source to drain. Near the drain, “hot” (high energy) electrons form and are attracted into the floating gate by the electric field from the control gate. After sufficient negative charge accumulates in the floating gate, the floating gate raises the threshold voltage of the memory cell and inhibits current flow through the channel region during subsequent “read” operations. The magnitude of the current when read voltages are applied to the gates is used to determine whether or not a flash memory cell is programmed.
The act of discharging a flash memory cell is called the erase function. For a floating gate memory cell, the erase function is typically carried out by inducing Fowler-Nordheim tunneling between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source region and a 0 V to the control gate and the substrate while floating the drain region.
An alternative to floating gate flash memory is SONOS-type flash memory. SONOS-type flash memory cells are constructed with a charge trapping dielectric layer, typically a silicon nitride layer, separated from the channel by a tunnel oxide, typically silicon dioxide. A control gate layer is formed over the charge trapping layer, and is optionally separated from the charge trapping layer by another dielectric layer, also typically silicon dioxide. The charge trapping layer holds charge, which represents data. Electrical charge is trapped within the layer locally near whichever side of the transistor is used as a drain in programming the cell. By reading in the opposite direction of programming, the presence or absence of charge at either side can be separately detected, whereby two bits of data can be stored per cell. Thus, a SONOS-type cell can be described as a two-transistor cell, or two-bit per cell architecture. If multi-level is used, then four or more bits per cell can be stored.
Storing two or more bits per cell provides a way of achieving high memory density.
Both bits of a SONOS-type memory cell are programmed in a conventional manner, such as hot electron programming. The right bit can be programmed by applying programming voltages to the gate and the drain while the source is grounded or at a lower voltage. Hot electrons are accelerated sufficiently so that they are injected into a region of the charge trapping dielectric layer near the drain. To read the device in the opposite direction from which it is written, voltages are applied to the gate and the source while the drain is grounded or at a lower voltage. The left bit is similarly programmed and read by swapping the functionality of source and drain terminals. Programming and reading one of the bits generally leaves the other bit with its information intact.
Reading in the reverse direction is most effective when relatively low gate voltages are used. A benefit of utilizing relatively low gate voltages in combination with reading in the reverse direction is that a relatively small trapped charge region, which affects the potential in the channel only beneath that region, is sufficient to significantly alter the potential drop needed for current to flow through the channel. Less charge needs to be stored, which permits much shorter programming times.
SONOS-type memory devices offer additional advantages as well. In particular, the erase mechanism of the memory cell is greatly enhanced. Both bits of the memory cell can be erased by applying suitable erase voltages to the gate and the drain for the right bit and to the gate and the source for the left bit. Another advantage is that SONOS-type memory cells undergo less wear from cycling and thus have greater longevity.
A potential disadvantage of SONOS-type memory is the length of time over which SONOS-type memory holds charge without power. In a typical SONOS-type memory cell, charge is gradually lost, most likely through pinhole defects in the silicon nitride film. There is an unsatisfied need for flash memory that has high density and can hold charge over more extended periods of time without power.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some of its aspects. This summary is not an extensive overview of the invention and is intended neither to identify key or critical elements of the invention nor to delineate its scope. The primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to flash memory devices that store charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si
3
N
4
)x(SiO
2
)
(1-x)
, where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices.
Another aspect of the invention relates to a process of forming a substantially stoichiometric silicon oxynitride layer for a flash memory device. The process involves assessing the stoichiometry and adjusting process conditions as needed to improve stoichiometry. In one embodiment, the stoichiometry is assessed from an FTIR spectrum. In another embodiment, the stoichiometry is assessed by measuring the refractive index at two or more wavelengths.
Other advantages and novel features of the invention will become apparent from the following detailed description of the invention and the accompanying drawings. The detailed description of the invention and drawings provide exemplary embodiments

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