Flash memory devices having three dimensional stack...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185180, C365S185250

Reexamination Certificate

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07843733

ABSTRACT:
Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.

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patent: 6317353 (2001-11-01), Ikeda et al.
patent: 7170786 (2007-01-01), Chien et al.
patent: 7551490 (2009-06-01), Kim
patent: 7596026 (2009-09-01), Kwon et al.
patent: 2005/0162927 (2005-07-01), Chien et al.
patent: 06-053517 (1994-02-01), None
patent: 2002-093184 (2002-03-01), None
patent: 2005-209271 (2005-08-01), None
Non-Final Rejection, Korean Application No. 10-2007-0057517, Aug. 26, 2008.

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