Flash memory devices and methods of operating the same

Details Flash memory devices and methods of operating the same Flash memory devices and methods of operating the same

2006-11-30

2008-12-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185230, C365S185330, C365S230060

Reexamination Certificate

active

07460403

ABSTRACT:
A memory cell array includes a NAND string formed of a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor. The string selection transistor controls an electrical connection between the NAND string and a bit line based on a string selection voltage in a read operation. A row selection circuit is coupled to the memory cell array through a string selection line, ground selection line and a plurality of word lines. The row selection circuit selects a word line which is coupled to the read memory cell among the plurality of word lines based on a row address signal and a read voltage in a read operation. A voltage generation circuit generates the string selection voltage and the read voltage.

REFERENCES:
patent: 6809365 (2004-10-01), Nakamura et al.
patent: 6987694 (2006-01-01), Lee
patent: 2006/0274564 (2006-12-01), Kim
patent: 100161410 (1998-08-01), None
patent: 100164354 (1998-09-01), None
patent: 10-0349355 (2002-08-01), None
patent: 10-2002-0094502 (2002-12-01), None
Korean Office Action (dated Nov. 26, 2007) for counterpart Korean Patent Application 10-2006-0102272 is provided for the purposes of certification under 37 C.F.R. §§ 1.97(e).

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