Flash memory devices and erasing methods thereof

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185330, C365S185180

Reexamination Certificate

active

08045382

ABSTRACT:
Disclosed is an erasing method for a flash memory device that includes erasing memory cells of a selected memory block and post-programming the erased memory cells to have a threshold voltage distribution with the lowest level that is at or near 0V. The post-programming includes first post-programming the memory block in the unit of memory block and second post-programming the memory block in the unit of word line.

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patent: 2005/0276120 (2005-12-01), Hsia et al.
patent: 2007/0076490 (2007-04-01), Kurata et al.
patent: 2010/0128523 (2010-05-01), Yip
patent: 10-228784 (1998-08-01), None
patent: 1020010037589 (2001-05-01), None
patent: 1020040008529 (2004-01-01), None

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