Flash memory device with program status detection circuitry...

Details Flash memory device with program status detection circuitry... Flash memory device with program status detection circuitry...

2000-09-06

2001-08-28

Fears, Terrell W (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S201000

Reexamination Certificate

active

06282121

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 1999-37725, filed on Sep. 6, 1999 and No. 2000-497, filed on Jan. 6, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to a NAND-type flash EEPROM (electrically programmable and erasable read only memory) device with program status detection circuitry and the method thereof.
BACKGROUND OF THE INVENTION
Programming a NAND-type flash EEPROM device is operable with the repetitive cycles of programming, data read-out, and program verifying, and Y-SCAN. Specifically, during the program cycle, EEPROM cells associated with a selected page (i.e., a word line) are programmed into a desired data state. The data read-out operation of the programmed cells is then performed. Finally, the verifying operation is carried out in order to check whether the programmed cells are situated in the desired data state. If at least one of the programmed cells does not correspond to the desired state, the above program cycles are continuously performed for predetermined times. To this end, most of flash memory devices include a program status detection circuit to determine PASS or FAIL, informing of a result of the programming.
A program status detection circuit for flash memories, for example, is disclosed in U.S. Pat. No. 5,299,162, entitled “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND AN OPTIMIZING PRGRAMMING METHOD THEREOF”.
FIG. 1
illustrates the program status detection circuitry disclosed in the above-mentioned document. Referring now to
FIG. 1
, each of bitlines BL
1
-BL
1024
is coupled to a NAND-structured cell string (CE) composed of a serial-connected transistor ST, eight cell transistors CT
1
-CT
8
, and a ground selection transistor GT. The string selection transistor ST and the ground selection transistor GT have a MOS transistor structure. Gates are coupled to selection lines SL
1
and SL
2
, respectively. Each of the cell transistors CT
1
-CT
8
has a structure of a depletion MOS transistor having a floating gate placed between a control gate and a substrate. Each control gate is coupled to each of the control lines CL
1
-CL
8
. Each of the bitlines (BL
1
-BL
1024
) is coupled to each of high voltage supply circuits HV for supplying program voltage with positively high level, each of bitline latch circuits LT on which externally inputted data is loaded, a current source circuit CS for supplying detection current during program detection operation, and each of program check units PC for inverting data of the bitline latch circuit LT.
The high voltage supply circuit HV is a charge pump circuit composed of transistors PT
1
and PT
2
and a pumping capacitor C
1
. A drain of the transistor PT
1
is coupled to program voltage Vpp, a gate thereof is coupled to a bitline BL
1
, and a source thereof is coupled to a gate of a transistor PT
2
. A drain of the transistor PT
2
is coupled to one electrode of a pumping capacitor C, and a source thereof is coupled to the bitline BL
1
. When a clock signal Øpp goes to high level, the pumping capacitor C discharges charge stored in a capacitor C to the bitline BL
1
through the transistor PT
2
and supplies erase voltage and program inhibit voltage to the bitline.
The bitline latch circuit LT is formed of two inverters INV
1
and INV
2
, and a transfer transistor TT
1
. The inverters INV
1
and INV
2
are coupled to each other, coupling an input of one of them to an output of the other. A gate of the transfer transistor TT
1
is coupled to a clock signal Ø
1
, a first current terminal (drain or source) thereof is coupled to a bitline, and a second terminal thereof (source or drain) is coupled to an input of the inverter INV
2
. Thus, the bitline latch circuit LT receives and holds external data applied to the bitline through the transfer transistor TT
1
being turned on when the clock signal Ø
1
is on high potential.
The current source circuit CS includes a plurality of output circuits OS coupled to each of bitlines and a common reference current setting circuit RC. The circuits RC and OS are coupled to each other in the form of a current mirror circuit so as to establish reference current against all the output circuits OS. The common reference current setting circuit RC comprises a P-channel MOS transistor M
1
, coupled between power supply voltage Vcc and ground voltage Vss, and N-channel MOS transistors M
2
and M
3
. A drain and a gate of the P-channel MOS transistor M
1
are coupled to each other. A gate of the N-channel MOS transistor M
2
is coupled to reference voltage Vref, and that of the N-channel MOS transistor M
3
is coupled to a clock signal Ø
2
. Each of the output circuits OS has a P-channel MOS transistor M
4
, coupled between the power supply voltage Vcc and each of the bitlines, and an N-channel MOS transistor M
5
. A gate of the P-channel MOS transistor is coupled to that of the P-channel MOS transistor. A gate of the N-channel MOS transistor M
5
is coupled to the clock signal Ø
2
. Thus, the current source circuit CS is enabled when the clock signal Ø
2
goes to a high level, so that drain current of the P-channel MOS transistor M
4
, i.e., verifying current, is supplied to the bitline BL
1
.
The program check circuit PC includes a MOS transistor M
6
. A drain of the MOS transistor M
6
is coupled to an input of the inverter INV
1
, a source thereof is coupled to the ground voltage Vss, and a gate thereof is coupled to a bitline. If the verifying current applied to the bitline dose not flow to a ground through a NAND-structured cell string including a selected cell, the bitline goes to high level and consequently the MOS transistor M
6
(program verifying unit) is turned on. This makes the input of the inverter INV
1
go to low level (e.g., ground voltage). Thus, when programming the selected cell is insufficient, the program check circuit PC detects an insufficient programming state and then invert a data logic level of the bitline latch circuit LT.
In
FIG. 1
, there is program status detection circuit PS. When all the selected cells are programmed with an optimal state, the circuit PS outputs a normal detection signal. When at least one of the selected cells is insufficiently programmed, the circuit PS outputs an abnormal detection signal. The circuit PS includes a P-channel MOS transistor M
7
and a depletion MOS transistor M
8
. The P-channel MOS transistor M
7
serves as a pull-up circuit for pulling up a node N
1
, and the depletion MOS transistor M
8
serves as a pull-up load. A source of the P-channel MOS transistor is coupled to the power supply voltage Vcc, a gate thereof is coupled to a clock signal Ø
3
, and a drain thereof is coupled to a source of the depletion MOS transistor M
8
. A gate and a drain of the depletion MOS transistor M
8
are coupled to the node N
1
. A plurality of N-channel MOS transistors PD
1
-D
1024
, serving as a pull-down circuit PD, are coupled between the node N
1
and a ground voltage Vss in parallel. A gate of each of the MOS transistors is coupled to an inverted output {overscore (Q)} of the bitline latch circuits LT. The node N
1
is coupled to one input terminal of a NOR-type gate G through an inverter INV
3
. The other of the NOR-type gate G is coupled to a clock signal {overscore (Ø
4
)}.
Program and verifying operations of the nonvolatile semiconductor memory device shown in
FIG. 1
will be described more fully hereinafter.
First, an erase operation for making a threshold voltage of a cell into a negative level is performed before programming data into a cell. After completion of the erase operation, external data is loaded on the bitline latch circuit LT. At this time, logic high level is loaded to data “1” and logic low level is loaded to data “0”. When the clock signal Ø
1
is at high level, the data is loaded on the bitline latch circuit LT. If the data held thereon is at high level, the high voltage supply circuit LT is operated to set a voltage on

Affiliated with

Also associated with

Rating

Flash memory device with program status detection circuitry... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flash memory device with program status detection circuitry..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory device with program status detection circuitry... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2473560