Flash memory device with multi level cell and burst access...

Details Flash memory device with multi level cell and burst access... Flash memory device with multi level cell and burst access...

2008-04-15

2008-04-15

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185130, C365S185230

Reexamination Certificate

active

11322983

ABSTRACT:
A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

REFERENCES:
patent: 7164602 (2007-01-01), Hamamoto et al.
patent: 2006/0087893 (2006-04-01), Nishihara et al.
patent: 08-315586 (1996-11-01), None
patent: 10-233096 (1998-09-01), None
patent: 2005-0007653 (2005-01-01), None
English language abstract of Korean Publication No. 2005-0007653.
English language abstract of Japanese Publication No. 08-315586.
English language abstract of Japanese Publication No. 10-233096.

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