Flash memory device with improved read speed

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185030, C365S185180, C365S189090

Reexamination Certificate

active

07405977

ABSTRACT:
A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select one of the rows and drive the selected row with a word line voltage, and voltage lines transmitting the respective read voltages to the row selecting circuit as the word line voltage. The read voltages are supplied to the respective voltage lines before starting read periods of the multi-bit read operation.

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patent: 6307783 (2001-10-01), Parker
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patent: 6768676 (2004-07-01), Hirano
patent: 6870785 (2005-03-01), Kang
patent: 2000-222894 (2000-08-01), None
patent: 2003-223791 (2003-08-01), None
patent: 2004319007 (2004-11-01), None
patent: 1020030009281 (2003-01-01), None
patent: 1020050025822 (2005-03-01), None

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