Flash memory device with a status read operation

Details Flash memory device with a status read operation Flash memory device with a status read operation

2000-06-13

2001-06-19

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189050, C365S189110

Reexamination Certificate

active

06249461

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 1999-23429, filed on Jun. 22, 1999 and No. 2000-27603, filed on May 23, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention is related to semiconductor memory devices, in particular, to a flash memory having means to indicate its status of operation.
BACKGROUND OF THE INVENTION
Electrically erasable and programmable flash memory of a conventional type is illustrated in
FIG. 1
in a block form. The memory is disclosed in a data book, entitled “Flash Memory”, published by SAMSUNG ELECTRONICS CO. Ltd, 3, 1998. As shown in
FIG. 1
, the flash memory includes an array
10
of electrically erasable and programmable memory cells, which are arranged at intersections of plural word lines and plural bit lines (not shown). One of the memory cells is schematically illustrated in
FIG. 2. A
memory cell of the electrically erasable and programmable flash memory comprises a cell transistor or a floating gate transistor, which has a source and a drain each formed in a p-type semiconductor substrate or a bulk, a floating gate formed over a channel region between the source and the drain with an insulator interposed therebetween, and a control gate formed over the floating gate with another insulator interposed therebetween.
The flash memory further comprises a row-address buffer & latch circuit
20
, a column-address buffer & latch circuit
30
, a pre decoder circuit
40
, a row selector circuit
50
, a column selector circuit
60
. A row of memory cells in the array
10
is selected by the row selector circuit
50
according to address signals which are provided from the row-address buffer & latch circuit
20
via the pre decoder circuit
40
. Columns of memory cells therein are selected by the column selector circuit
60
according to address signals which are provided from the column-address buffer & latch circuit
30
via the pre decoder circuit
40
.
Each of the memory cells in the selected row and columns is programmed under the bias condition that a ground voltage (e.g., 0 V) is applied to its source and its substrate, a high voltage (e.g., +10 V from a program voltage generator
90
) to its control gate, and a positive voltage (e.g., +5 V to +6 V) suitable to generate hot electrons to its drain. According to the bias condition, the sufficient amount of negative charges is accumulated in the floating gate and thereby the floating gate has (−) potential. This forces the threshold voltage of the programmed cell transistor to be increased during a read operation. During the read operation, a state of the memory cell is discriminated by a sense amplifier
110
as an “OFF” state, and its threshold voltage is distributed in a range of +7 V to +9 V, as shown in FIG.
3
. The above-described program operation is performed under the control of a control logic & command register circuit
70
.
As well known, the array
10
of the flash memory is divided into a plurality of sectors. The bulk regions of the respective sectors are electrically separated from each other, and memory cells integrated in each sector are simultaneously erased during an erase operation.
Each of memory cells in a selected selector is erased by the Fowler-Nordheim tunneling mechanism. According to the F-N tunneling mechanism, a negative high voltage (e.g., −10 V from an erase voltage generator
100
) is applied to the control gate, a positive voltage (e.g., +5 V to +6 V) suitable to make the F-N tunneling is applied to the semiconductor substrate of the bulk, and the source and the drain are maintained at a floating state. The erase operation of such a bias condition is referred to as “Negative Bulk and Gate Erase” operation. By the bias condition, strong electric field of 6 to 7 MV/cm is made between the control gate and the semiconductor substrate. As a result, negative charges accumulated in the floating gate are discharged through the insulator having the thickness of about 100
66
(angstrom). This makes the threshold voltage of the erased cell transistor lowered during the read operation. During the read operation, a state of the memory cell is discriminated by the sense amplifier
110
as an “ON” state, and its threshold voltage is distributed in a range of +1 V to +3 V, as illustrated in FIG.
3
. Similarly, the above-described erase operation is performed under the control of the control logic & command register circuit
70
.
As well known in the art, a time required to erase memory cells in a sector and to program memory cells is longer than that required to read data from memory cells. For instance, an erase time is about one second, a read time is about 100 ns (nanosecond), and a program time is about 10 us (microsecond). In the flash memory is provided a suspend mode of operation in which an erase operation for a sector is suspended while a program or read operation for another sector can be performed. That is, the suspend mode of operation is provided to the flash memory as a system interrupt function. The suspended erase operation is resumed after completing the read or program operation for another sector.
In the flash memory is also provided a status read operation in order for an user to confirm its status of operation. The status of operation for the flash memory can be judged to use values of five data input/output pins DQ
2
, DQ
3
, DQ
5
, DQ
6
, and DQ
7
or a value of a pin R/B#. The symbol # is to indicate an active low signal. During the status read operation, the values of the data input/output pins are changed as an output enable signal OE# is toggled in synchronization with a read timing. The statuses are as follows.
TABLE 1
Operation
DQ7
DQ6
DQ5
DQ3
DQ2
R/B#
Standard Mode
Program
DQ7#
Toggle
0
N/A
No
0
toggle
Erase
0
Toggle
0
1
Toggle
0
Erase Suspend Mode
Read within erase
1
No
0
N/A
Toggle
1
suspended sector
toggle
Read within non-
Data
Data
Data
Data
Data
1
erase suspended
sector
Erase suspend
DQ7#
Toggle
0
N/A
N/A
0
program
In the table, a symbol N/A indicates “not available”. As shown in the table, the values of the pins R/B#, DQ
2
, DQ
3
, DQ
5
, DQ
6
, and DQ
7
are toggled or maintained at a previous value according to a mode of operation. As illustrated in
FIG. 4
, for example, when an erase operation is performed, the values of the pins DQ
2
and DQ
6
are toggled as the signal OE# is toggled. When an erase operation is suspended and then a read operation is performed, the value of the pin DQ
2
is toggled while the value of the pin DQ
6
is maintained at a previous state. As seen from the above description, the status read operation is performed by toggling the signal OE# after an input of a command for an erase/program operation.
FIG. 5
shows an output enable buffer illustrated in FIG.
1
. The output enable buffer
130
is composed of a NOR gate G
1
and two inverters INV
1
and INV
2
connected as illustrated in FIG.
5
. When the output enable signal OE# is at a high level as an inactive state, output signals POE and OE have a low level, respectively. On the other hand, when the output enable signal OE# is at a low level as an active state, the signals PEO and OE have a high level, respectively.
In
FIG. 6
, a conventional data output circuit comprised in the circuit
122
is illustrated which is associated with a data input/output pin whose value is toggled in the synchronization with the output enable signal OE# during the status read operation. As seen from the table, the values of the pins DQ
2
and DQ
6
are toggled as the signal OE# is toggled during an erase operation. During the program operation, the value of the pin DQ
2
is not toggled while the value of the pin DQ
6
is toggled. In
FIG. 6
, the data output circuit associated with the pin DQ
2
is illustrated, but that associated with the pin DQ
6
, whose value is toggled according to the signal OE#, is also configured the same as FIG.
6
. The data output ci

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