Flash memory device operating at multiple speeds

Details Flash memory device operating at multiple speeds Flash memory device operating at multiple speeds

2011-03-01

2011-03-01

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S230030

Reexamination Certificate

active

07898871

ABSTRACT:
A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.

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