Flash memory device isolation method and structure

Details Flash memory device isolation method and structure Flash memory device isolation method and structure

1998-03-12

2000-09-19

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438297, 438439, 438257, H01L 2176

Patent

active

061211168

ABSTRACT:
The present invention provides novel isolation regions (501, 215) in a flash memory integrated circuit device. The isolation regions (501, 215) are formed on a silicon substrate (201), which has a core memory region (e.g., flash memory cell region) and a high voltage region (e.g., high voltage MOS device region). A silicon dioxide layer (e.g., silicon dioxide, silicon oxynitride) (203) is defined overlying the substrate including both of the regions. A nitride mask layer (205) is formed overlying the silicon dioxide layer in the core memory region and the high voltage region. This nitride mask layer exposes (207) a first isolation region coupled to the high voltage region. The first isolation region includes a first isolation structure having a first thickness of silicon dioxide. A step of oxidizing an exposed second isolation region to form the second isolation structure (215) and simultaneously oxidizing the first isolation structure to a second thickness is included.

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