Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2003-08-04
2004-10-26
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S049130, C365S230060
Reexamination Certificate
active
06809973
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flash memory device capable of repairing a word line, and more particularly, to a flash memory device capable of repairing a word line, which can repair fail word lines in a main cell array using a bit line redundancy cell array.
2. Background of the Related Art
In general, if fail occurs in the flash memory cell array due to defect, etc., the fail cell is replaced with an extra cell in order to prevent reduction in the yield. For this purpose, a bit line redundancy cell array in addition to a main cell array is provided in the flash memory device. The redundancy cells are only used to repair fail or single cell fail in the direction of the bit line for the most part. Accordingly, in the prior art, in case where fail occurred in the direction of the word line, one chip is treated as fail without a special repair method.
Meanwhile, in case where fail occurred in the direction of the word line, the word line redundancy cell array having the same number to the number of the cells connected to one the word line must be provided in the main cell array in order to repair fail. In this case, there are problems that lots of areas are required and it is difficult to integrate the device, since the width of the word line redundancy cell array must be same to that of the main cell array. Furthermore, in case where cells that are failed in the direction of the word line are repaired within the sector, the cells of the word line that are failed upon erasing the sector are over erased while they are continuously erased. Due to this, the leakage current is generated in the bit line and all the cells formed in the same well region could not be thus used.
In particular, in a prior art that the word line is repaired within the flash EEPROM sector array, the same bias is applied to the word line and the P well in order to repair the word line. In this case, however, repair is performed in a word line to word line mode. Accordingly, there are disadvantages that a well region of the word line redundancy cell array and a well region of the main cell array have to be separated in order to block the leakage current occurring by the fail cell and the chip size is increased.
SUMMARY OF THE INVENTION
Accordingly, the present invention is contrived to substantially obviate one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a flash memory device capable of repairing a word line, which can prevent degradation in the yield and improve reliability of the device, in such a manner that fail word lines are repaired using redundancy cells for repairing bit lines by combining x/Y addresses, thus allowing repair in the direction of the bit line as well as repair in the direction of the word line.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a word line repair circuit in a flash memory device according to one embodiment of the present invention is characterized in that it comprises a main cell array in which a plurality of cell are classified in a I/O block unit, a redundancy cell array consisting of repair blocks in which the number of word lines is equivalent to the number of columns constituting the I/O block and the number of cells connected to the word line is equivalent to the number of the I/O block, a CAM cell array for storing information including information on a fail word line of the main cell array and connection information on the repair block instead of the fail word line, a word line voltage switching unit for transferring a word line voltage applied to the fail word line to the redundancy cell array according to information on the fail word line, and a word line select means enabled by the connection information, for selecting a word line of the repair block corresponding to a column of the I/O block according to the column select signal of the main cell array and then applying the word line voltage to the selected word line, wherein data to be stored through the fail word line are sequentially stored through a corresponding column of the repair block in a I/O block unit, thereby repairing the fail word line.
In the above, the I/O block may be 16 in number. At this time, the I/O block may include 1024 word lines and 64 columns and the repair block may include 64 word lines and 16 columns.
Meanwhile, the word line voltage switching unit comprises first switching means each connected between the word line voltage supply terminal and the word line of the main cell array and driven by a fail word line signal of the CAM cell array;
an inverter for inverting the fail word line signal, and a second switching means for transferring the word line voltage to the word line select means according to the fail word line inverted signal from the inverter. At this time, the first switching means and the second switching means may be field effect transistors.
The word line select means is provided every repair block. The word line select means comprises a first switching means driven by an enable signal depending on the connection information stored at the CAM cell array, for switching the word line voltage, and a plurality of switching means each connected between the first switching means and the word line of the repair block, for switching the word line voltage to a word line of a repair block corresponding to a corresponding column according to the column select signal of the main cell array.
In another aspect of the present invention, it is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5200922 (1993-04-01), Rao
patent: 5774396 (1998-06-01), Lee et al.
patent: 6385071 (2002-05-01), Chai et al.
patent: 693 24 694 (1995-06-01), None
patent: 695 00 143 (1995-09-01), None
patent: 2 254 173 (1992-09-01), None
patent: 2 308 693 (1997-07-01), None
Hynix / Semiconductor Inc.
Lam David
Marshall & Gerstein & Borun LLP
LandOfFree
Flash memory device capable of repairing a word line does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flash memory device capable of repairing a word line, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory device capable of repairing a word line will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3332798