Flash memory device capable of reducing read time

Details Flash memory device capable of reducing read time Flash memory device capable of reducing read time

2006-08-01

2006-08-01

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S233500

Reexamination Certificate

active

07085169

ABSTRACT:
A flash memory device is disclosed that includes a control circuit for generating a count-up pulse signal notifying a generation of an address required for a burst read operation. An address generator circuit generates an address in response to the count-up pulse signal, and a discharge circuit discharges global bit lines in response to the count-up pulse signal. According to this control scheme, the global bit lines may be discharged before the local and global bit lines are selected.

REFERENCES:
patent: 5642324 (1997-06-01), Ghosh et al.
patent: 5798976 (1998-08-01), Arimoto
patent: 6046940 (2000-04-01), Takeuchi et al.
patent: 6097638 (2000-08-01), Himeno et al.
patent: 6147910 (2000-11-01), Hsu et al.
patent: 6288953 (2001-09-01), Kwak
patent: 6507900 (2003-01-01), Okajima
patent: 6862247 (2005-03-01), Yamazaki

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