Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-09-13
2002-10-22
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185180, C365S185190
Reexamination Certificate
active
06469933
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 2000-069534, filed on Nov. 22, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to non-volatile memory devices and more particularly to a method for programming a NAND-type flash memory device using a self-boosting technique.
BACKGROUND OF THE INVENTION
A flash memory device, known as a flash EEPROM (electrically erasable programmable read-only memory), typically includes an array of memory cells formed of floating gate transistors. The array includes strings (or, “NAND strings”) of the floating gate transistors, and each of the floating gate transistors is connected between a string selection transistor and a ground selection transistor arranged in a series within each of the strings. A plurality of word lines are intersectionally arranged in the NAND strings, each being connected to a control gate of the floating gate transistors corresponding thereto.
Initially, the floating gate transistors, i.e., memory cells, are erased, for example, to have at a lower threshold voltage, e.g. −3V. To program a given memory cell, a high voltage (e.g., 20V) is applied to the word line of a selected memory cell for a predetermined time, so that the selected memory cell is changed to have higher threshold voltage. Meanwhile, threshold voltages of the unselected memory cells do not change.
There is a problem in programming the selected memory cell connected to a predetermined word line without programming the unselected memory cells connected to the same word line. When a program voltage is applied to the word line, the voltage is also applied to the unselected memory cells arranged along the same word line as well as the selected memory cell. Thus, the unselected memory cells connected to the word line, and in particular, the memory cell adjacent to the selected memory cell is programmed. Such unintentional programming of one or more unselected memory cells is called “program disturb”.
A conventional method to prevent the program disturb problem is a program inhibition method employing a self-boosting scheme. The program inhibition method using the self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873 entitled “Method of Programming Flash EEPROM Integrated Circuit Memory Devices To Prevent Inadvertent Programming of Nondesignated NAND Memory Cells Therein”, and U.S. Pat. No. 5,991,202 entitled “Method for Reducing Program Disturb During Self-Boosting in a NAND Flash Memory”, which are incorporated herein by these references.
In the program inhibition method using the self-boosting scheme, a ground path is blocked by applying 0V to the gate of a ground selection transistor. Zero V is applied to a selected bit line, while a power supply voltage Vcc of 3.3V or 5V is applied as a program inhibition voltage to an unselected bit line. At the same time, after the source of a string selection transistor is charged to Vcc-Vth (Vth: a threshold voltage of the string selection transistor) by applying the power supply voltage to the gate of the string selection transistor, the string selection transistor is virtually blocked. And then, a channel voltage of the program inhibited cell transistor is boosted by applying the program voltage Vpgm to the selected word line, and pass voltage Vpass to the unselected word lines. Thus, Fowler-Nordheim (F-N) tunneling cannot take place between the floating gate and the channel, thereby keeping the program inhibited cell transistor in the initial erased state.
Another conventional program inhibition method employs a local self-boosting scheme. The method is disclosed in U.S. Pat. No. 5,715,194 entitled “Bias Scheme of Program Inhibit for Random Programming In a NAND Flash Memory”, and U. S. Pat. No. 6,061,270 entitled “Method for Programming a Non-volatile Memory Device with Program Disturb Control”, which are incorporated herein by these references.
In the program inhibition method utilizing the local self-boosting scheme, 0V is applied to two unselected word lines adjacent to the selected word line. After the pass voltage Vpass (e.g., 10V) is applied to the other unselected word lines, the program voltage Vpgm is applied to the selected word line. According to the bias scheme, the channel of a self-boosted cell transistor is confined to the selected word line, and the channel boosting voltage of the program inhibited cell transistor is increased more than that of the foregoing method using the self-boosting scheme. Thus, the F-N tunneling cannot take place between the floating gate and the channel of the program inhibited cell transistor, thereby keeping the transistor in the initial erased state.
In the conventional program inhibition methods utilizing the self-boosting scheme or the local self-boosting scheme, however, the program disturb phenomenon increasingly occurs in accordance with an increasing density of the flash memory device. Intervals between adjacent signal lines are reduced due to the increasing integration density; thereby more easily generating couplings between the adjacent signal lines. For example, if a memory cell adjacent to the string selection transistor is programmed, the voltage on the string selection line (e.g., the power supply voltage) is boosted due to the capacitive coupling with the word line when the program voltage is applied to the selected word line. The rising voltage of the string selection line causes charges in the channel of the program inhibited cell transistor to go out to the unselected bit line through the string selection transistor being turned on by the rising voltage from the shut-off state, resulting in reducing the channel voltage of the program inhibited cell transistor. Consequently, the program disturb problem remains.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a flash memory device capable of preventing a program inhibited memory cell from being soft-programmed during program operation, and a method for programming the device.
In order to attain the above object, according to an aspect of the present invention, there is provided a non-volatile memory device, having a plurality of memory cells arranged in matrix, a first and second selection transistors for selecting a memory cell, a plurality of bit lines connected to drains of the memory cells, and a plurality of word lines connected to control gates of the memory cells. In a method for programming the non-volatile memory device, a ground voltage is applied to a first bit line corresponding to the memory cell to be programmed, and a power supply voltage is applied to a second bit line corresponding to a memory cell to be prevented from being programmed. Then, a program voltage is applied to a first word line connected to the memory cell to be programmed. The program voltage is stepped up to a desired voltage level of each program cycle from the first voltage.
According to another aspect of this invention, there is provided a NAND-type flash memory device including a memory cell array, having a plurality of strings each of which is formed of a first selection transistor, a second selection transistor, and plural memory cells connected between the selection transistors in series, a plurality of bit lines connected to the plurality of strings corresponding thereto, and a plurality of word lines electrically connected to the memory cells of the strings, and a selection signal generating circuit creating a selection signal to select one of the word lines during a programming operation. The selection signal generating circuit creates the selection signal that is stepped up from ground voltage to a desired voltage of each program cycle.
The selection signal generating circuit includes: a switch pump receiving a program voltage having the desired voltage level of each program cycle and generating the program voltage in response to an oscillation signal provided from an oscillation circuit; a signal generator providing the selection signal
Choi Sun-Mi
Lee Yeong-Taek
Lim Young-Ho
Hoang Huan
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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