Flash memory device capable of minimizing a substrate...

Details Flash memory device capable of minimizing a substrate... Flash memory device capable of minimizing a substrate...

2000-06-20

2002-03-05

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185290

Reexamination Certificate

active

06353555

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit devices. More particularly it concerns a NAND-type flash memory device made less susceptible to program disturb or underprogramming by reducing substrate voltage bounce, and a method of programming such an improved device.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram of a conventional NAND-type flash memory device. The conventional flash memory device comprises an array divided into a plurality of memory blocks BLK
1
through BLKi. In the flash memory device, a plurality of bit lines BL
1
through BLj are arranged to extend in parallel through the memory blocks BLK
1
through BLKi. In each memory block BLK
1
through BLKi, a plurality of strings are provided which correspond to the bit lines BL
1
through BLj, respectively. Each of the strings in the respective memory blocks BLK
1
through BLKi comprises a first string select transistor ST
1
, a second string select transistor ST
2
, and a plurality of, for example, sixteen flash EEPROM cell transistors M
1
through M
16
connected in series between a source of the first string select transistor ST
1
and a drain of the second string select transistor ST
2
. A drain of the first string select transistor ST
1
in each string is connected to a corresponding bit line, and a source of the second string select transistor ST
2
therein is coupled to a common source line (a common signal line) CSL.
Gates of the first string select transistors ST
1
in the strings are coupled in common to a first string select line SSL
1
, and gates of the second string select transistors ST
2
therein are coupled in common to a second string select line SSL
2
. Control gates of the flash EEPROM cell transistors in each string are coupled in common to a corresponding one of the word lines WL
1
through WL
16
. Each of the bit lines BL
1
through BLj is electrically coupled to a page buffer circuit
10
. As is well known to ones skilled in the art, the page buffer circuit
10
includes a plurality of page buffers (not shown) corresponding to the bit lines BL
1
through BLj, respectively, each page buffer having a latch (not shown).
Referring still to
FIG. 1
, the conventional NAND-type flash memory device further comprises a plurality of block select control circuits
20
_
1
through
20
_i, which are arranged so as to correspond to the memory blocks BLK
1
through BLKi, respectively. Each of the block select control circuit
20
_
1
through
20
_i is composed of a block select signal generator
22
(serving as a block select decoder) for generating a block select signal such as BSEL
1
in response to a block select address, and a plurality of select transistors BT
1
through BT
18
connected as illustrated in FIG.
1
. The transistors BT
1
through BT
18
(referred to herein as a switch portion) are simultaneously turned on/off in response to the block select signal, e.g. BSEL
1
. A plurality of drive lines SS
1
, CG
1
through CGl
6
, and SS
2
coupled to a drive circuit
30
(serving as a word line decoder) are arranged in parallel via the block select control circuits
20
_
1
through
20
_i. In other words, the drive lines SS
1
, CG
1
through CG
16
, and SS
2
are shared by the block select control circuits
20
_
1
through
20
_i.
To select a memory block BLK
1
which has the EEPROM cell transistors for programming, a block select signal BSEL
1
corresponding to the selected memory block BLK
1
is activated high. This causes the select transistors BT
1
through BT
18
of the block select control circuit
20
_
1
(corresponding to the selected memory block BLK
1
) to be turned on at the same time. On the other hand, block select signals BSEL
1
through BSELi corresponding to de-selected memory blocks BLK
2
through BLKi are deactivated, turning off the select transistors BT
1
through BT
18
of the block select control circuits
20
_
2
through
20
_i. As a result, the first string select line SSL
1
, the word lines WL
1
through WL
16
and the second string select line SSL
2
of the selected memory block BLK
1
are electrically coupled to the corresponding drive lines SS
1
, CG
1
through CG
16
and SS
2
, whereas the lines SSL
1
, WL
1
-WL
16
and SSL
2
of each of the de-selected memory blocks BLK
2
through BLKi are in a float or high-impedance state.
FIG. 2
is a timing diagram that illustrates a program operation of a conventional NAND-type flash memory device. The program operation of the conventional NAND-type flash memory device will be more fully described below with reference to the accompanying drawings.
As illustrated in
FIG. 2
, the program cycle is divided into a bit line setup period, a program period, a recovery (or discharge) period, and a verify period. Before the bit line setup period, all of the latches of the page buffer circuit
10
are first serially loaded with program data: “0” for cells to be programmed and “1” for cells to be program-inhibited. If a memory block BLK
1
is selected, a block select signal BSEL
1
is activated by the block select signal generator
20
_
1
, so that the first string select line SSL
1
, the word lines WL
1
through WL
16
and the second string select line SSL
2
of the selected memory block BLK
1
are electrically coupled to the corresponding drive lines SS
1
, CG
1
through CG
16
and SS
2
via the corresponding select transistors BT
1
through BT
18
.
The bit lines BL
1
through BLj are charged at a power supply voltage VCC or at a ground voltage VSS, depending on the program data thus loaded during the bit line setup period. For example, a bit line coupled to an EEPROM cell transistor to be programmed is charged at the ground voltage VSS, and a bit line coupled to an EEPROM cell transistor to be program-inhibited is charged at the power supply voltage VCC. The first string select line SSL
1
of the selected memory block BLK
1
is coupled to the corresponding drive line SS
1
so as to be charged with the power supply voltage VCC, and the second string select line SSL
2
thereof is coupled to the corresponding drive line SS
2
so as to be charged at the ground voltage. The word lines WL
1
through WL
16
of the selected memory block BLK
1
are maintained at the ground voltage VSS level, and the word lines WL
1
through WL
16
(labeled WLs in
FIG. 2
) of the deselected memory blocks BLK
2
through BLK
1
are maintained in a float state, as illustrated in FIG.
2
.
During the program period, a selected word line WL
1
of the selected memory block BLK
1
is set to the program voltage V
pgm
(e.g. 15.5V-20V) via the drive line CG
1
and the select transistor BT
2
and each of the de-selected word lines WL
2
through WL
16
therein is set to the pass voltage V
pass
(e.g. 10V) via a corresponding drive line and select transistor. This produces a bias condition sufficient to cause Fowler-Nordheim tunneling of hot electrons from the drain side into a floating gate of an EEPROM cell transistor and EEPROM cell transistors coupled to the bit lines charged with the ground voltage VSS thus are programmed.
On the other hand, an EEPROM cell transistor which is coupled to the bit line charged with the power supply voltage VCC is program-inhibited. In particular, since the bit line and the gate of the first string select transistor ST
1
are set to the power supply voltage VCC, a source of the first string select transistor ST
1
is driven to a potential of approximately VCC-Vth, where Vth is the threshold voltage of the transistor ST
1
. However, once the source of the first string select transistor ST
1
reaches a potential of about VCC-Vth, the first string select transistor ST
1
is turned off (shut off). When this occurs, the source, drain and channel regions of the EEPROM cell transistors M
1
through M
16
become electrically disconnected from the bit line charged with the power supply voltage VCC and enter a floating state. Moreover, because the source, drain and channel regions of the EEPROM cell transistors M
1
through M
16
are capacitively coupled to their respective control gates WL
1
through WL
16
, the

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