Flash memory device and program method thereof

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180

Reexamination Certificate

active

07376017

ABSTRACT:
A flash memory device which comprises a memory cell array having memory cell arranged in rows and columns; a word line voltage generator circuit configured to generate a program voltage, a dielectric breakdown prevention voltage, and a pass voltage at a program operation; and a row selector circuit that receives the program voltage, the dielectric breakdown prevention voltage, and the pass voltage and selecting one of the rows in response to a row address. The dielectric breakdown prevention voltage is lower that the program voltage and higher than the pass voltage; and the row selector circuit drives the selected row with the program voltage, drives at least one row just adjacent to, or neighboring, the selected row with the dielectric breakdown prevention voltage and drives remaining rows with the pass voltage.

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patent: 10-2004-0036015 (2004-04-01), None

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