Flash memory device and method in which trim information is...

Details Flash memory device and method in which trim information is... Flash memory device and method in which trim information is...

2008-07-02

2010-10-26

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185010

Reexamination Certificate

active

07821836

ABSTRACT:
A flash memory device which includes a memory cell array which stores data and trim information, and control logic which controls programming, erasing, and reading modes of the memory cell array. The control logic is operative to receive the trim information from the memory cell array in a power-up mode, and to optimize operational time periods of the programming, erasing, and reading modes in accordance with the trim information.

REFERENCES:
patent: 7130227 (2006-10-01), Nobunaga et al.
patent: 2007/0253254 (2007-11-01), Morooka et al.
patent: 1020030023341 (2003-03-01), None
patent: 1020050041608 (2005-05-01), None
patent: 1020050056376 (2005-06-01), None
patent: 1020060099139 (2006-09-01), None

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