Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-09-30
2001-05-29
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S257000, C438S211000, C438S593000, C438S594000
Reexamination Certificate
active
06239009
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device and, more particularly, to a flash memory device and a method for manufacturing the same.
2. Background of the Related Art
General memory devices are divided into a read only memory (hereinafter referred to as ROM) and a random access memory hereinafter referred to as RAM). ROMs are divided into a mask ROM and a programmable ROM (PROM). In a mask ROM, a program data is inputted into a mask in advance to program the ROM. In a PROM, a chip is fabricated and mounted and then a ROM is programmed.
A PROM is again divided into an erasable programmable read only memory (EPROM) and an electrically erasable programmable read only memory (EEPROM). In an EPROM, inputted data can be erasable by means of ultraviolet ray. In an EEPROM, inputted data can be electrically erasable.
In a flash memory device of a three layered gate type, an erase gate is formed in an EEPROM cell so that inputted data may be electrically erasable. Also, in a flash memory device of a two layered gate type, an electric field is emitted toward a source.
FIG. 1
a
is a plan view of a related art flash memory device,
FIG. 1
b
is a cross-sectional view showing the structure of the related art flash memory device, taken along line I-I′ of
FIG. 1
a,
FIG. 1
c
is a cross-sectional view showing the structure of the related art flash memory device, taken along line II-II′ of
FIG. 1
a,
and
FIG. 1
d
is an equivalent circuit diagram of
FIG. 1
a.
A related art flash memory device, as shown in
FIGS. 1
a
to
1
c,
includes a plurality of buried heavily doped impurity regions
2
spaced away from one another by a predetermined distance by implanting heavily n
+
type impurity ions into a p-type semiconductor substrate
1
. A plurality of isolation oxide layers
3
is formed at a right angle to the plurality of the buried heavily doped impurity regions
2
. First sidewall spacers
3
a
are formed on both sides of each of the isolation oxide layers
3
, and a gate oxide layer
4
is formed on the entire surface of the semiconductor substrate
1
exclusive of the isolation oxide layers
3
and the first sidewall spacers
3
a.
Each of the floating gates
5
b
overlaps each of the buried heavily doped impurity regions
2
by a predetermined area, and a first interlevel insulating film
6
is formed on the entire surface of the semiconductor substrate
1
inclusive of the floating gates
5
b.
A control gate line
7
a
and a cap oxide layer
8
are successively formed on the first interlevel insulating film
6
and have a narrower width than the floating gate
5
b.
Second sidewall spacers
9
are formed on both sides of the control gate line
7
a
and the cap oxide layer
3
, and an erase gate line
11
a
overlapping two of the control gate lines
7
a.
One erase gate line
11
a
is designed to erase electrons of the floating gate
5
b
formed along the erase gate line
11
a.
For programming a flash memory of three layered polysilicons
5
b,
7
a,
and
11
a,
a voltage of 7V is applied to the buried heavily doped impurity region
2
, a voltage of 12 V is applied to the control gate
7
a,
and a voltage 0V is applied to the buried heavily doped impurity region
2
, which is neighboring with the buried heavily doped impurity region
2
used as the drain. Channel hot electrons, which are generated by high electric field at the drain of a channel, pass over potential barrier of the gate oxide layer
4
so as to be injected to the floating gate
5
b.
As a result, a threshold voltage of a memory device is increased.
For erasing inputted data, a high voltage of between 12V-24V is applied to the erase gate
11
a
and a voltage of 0V is applied to the control gate
7
a
and the floating gate
5
b.
Accordingly, a high electric field is generated due to a sharp geometrical structure of the floating gate
5
b
formed on the isolation oxide layer
3
and electrons travel to the erase gate
11
a,
thus generating an electron tunneling known as “Fowler Nordheim tunneling” from the floating gate
5
b
to the erase gate
11
a.
In other words, the floating gate
5
b
loses electrons and the threshold voltage of the memory device is decreased. The arrow shown in
FIG. 1
c
indicates the electron movement direction during the erase operation. Accordinaly, a threshold voltage of a device is controlled and inputted data is maintained. For reading data, voltages of 5V, 1V, and 0V are applied to the control gate, the drain, and the source and the erase gate, respectively, so that changes of potential of a bitline connected to the drain, or changes of current are sensed, depending on a difference of threshold voltages according to stored data, thereby reading the stored data.
FIGS. 2
a
through
2
i
are cross-sectional views showing process steps of the related art method for manufacturing the flash memory device, taken along line I-I′ of
FIG. 1
a.
FIGS. 3
a
through
3
i
are cross-sectional views showing process steps of the related art method for manufacturing the flash memory deice, taken alone line II-II′ of
FIG. 1
a.
First, heavily n
+
impurity ions are selectively implanted into a p-type semiconductor device
1
so as to form a plurality of buried heavily doped impurity regions
2
used as source and drain, as shown in
FIGS. 2
a
and
3
a.
At this time, the impurity regions
2
are spaced away from one another by a prescribed distance. An oxide layer is formed on the semiconductor substrate
1
and then is selectively patterned with a photolithography process and an photo etching process, thus forming a plurality of isolation oxide layers
3
at a right angle to the buried heavily doped impurity regions
2
. Next, first sidewall spacers
3
a
are formed on both sides of each of the isolation oxide layers
3
.
Referring to
FIGS. 2
b
and
3
b,
a gate oxide layer
4
is formed on the entire surface of the semiconductor substrate
1
exclusive of the isolation oxide layers
3
and the first sidewall spacers
3
a.
Then, on the entire surface, a polysilicon layer
5
which will be used as a floating gate is deposited.
Referring to
FIGS. 2
c
and
3
c,
a photoresist PR
1
is coated on the polysilicon layer
5
and then is subjected to exposure and development to pattern and to define the placement of a floating gate line. With the photoresist pattern PR
1
serving as a mask, the polysilicon layer
5
is selectively etched, and thus forming a floating gate line
5
a.
At this time, one edge of the floating gate line
5
a
overlaps the heavily doped impurity region
2
used as a drain by a predetermined area. The floating gate line
5
a
is offset from the heavily impurity region
2
used as a source.
Referring, to
FIGS. 2
d
and
3
d,
the remaining photoresist film PR
1
is removed. Subsequently, a first interlevel insulating film
6
, a polysilicon layer
7
used as a control gate, a cap oxide layer
8
, and a photoresist film PR
2
are successively formed on the entire surface of the semiconductor substrate
1
inclusive of the floating gate line
5
a,
the isolation oxide layer
3
, and the first sidewall spacers
3
a.
Thereafter, the photoresist film PR
2
is subjected to exposure and development to be patterned, thus defining a placement of a control gate line.
Referring to
FIGS. 2
e
and
3
e,
with the photoresist pattern PR
2
, serving as a mask, the cap oxide layer
8
, the polysilicon layer
7
, and the first interlevel insulating film
6
are selectively removed to form a control gate line
7
a.
At this time, the control gate line
7
a
is located between the isolation oxide layers
3
in the same direction as the isolation oxide layers
3
. Both edges of the control gate line
7
a
overlap the isolation oxide layers
3
by a predetermined area.
Referring to
FIGS. 2
f
and
3
f,
the remaining photoresist film PR
2
is removed. An oxide layer used as sidewall spacers is deposited on the entire surface of the semiconductor substrate
1
and then is etched-back to form second sid
Choi Jong Moo
Kim Sung Ryul
Park Young Keun
Fleshner & Kim LLP
Guerrero Maria
Hyundai Electronics Industries Co,. Ltd.
Meier Stephen D.
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