Flash memory device and layout method of the flash memory...

Details Flash memory device and layout method of the flash memory... Flash memory device and layout method of the flash memory...

2009-07-21

2011-10-18

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180, C365S185260, C365S185290

Reexamination Certificate

active

08040726

ABSTRACT:
Provided is a flash memory device including a plurality of page buffer high voltage transistors. The plurality of high voltage transistors are operatively associated with a page buffer circuit, wherein each high voltage transistor includes; a gate pattern separating a first pattern from a second pattern. The first and second patterns extend in parallel and serve as respective source/drain regions, and the first pattern is floated and the second pattern receives an erase voltage during an erase operation. A first set of high voltage transistors is series connected in a columnar arrangement, such that column adjacent high voltage transistors are laid out with alternating source/drain symmetry in the columnar direction.

REFERENCES:
patent: 6914813 (2005-07-01), Chevallier et al.
patent: 7787301 (2010-08-01), Lee et al.
patent: 7804716 (2010-09-01), Kwak et al.
patent: 1020050052808 (2005-06-01), None
patent: 1020060126165 (2006-12-01), None
patent: 100694972 (2007-03-01), None

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