Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-03
2001-11-27
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S257000
Reexamination Certificate
active
06323516
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to an integrated circuit (“IC”). More specifically, this invention relates to the fabrication of an integrated circuit having an improved coupling capacitance.
DESCRIPTION OF THE PRIOR ART
The present invention applies particularly to the fabrication of non-volatile memory integrated circuits. Some examples of non-volatile memory integrated circuits include an EPROM, an EEPROM, a flash memory device, and a complementary metal oxide silicon (“CMOS”) type device, such as a field-effect transistor (“FET”) containing a metal gate over thermal oxide over silicon (“MOSFET”) and other ultra-large-scale integrated-circuit (“ULSI”) systems.
Non-volatile memory integrated circuits are utilized in a wide variety of commercial and military electronic devices, including, e.g., hand held telephones, radios and digital cameras. The market for these electronic devices continues to demand devices with a lower voltage, a lower power consumption and a decreased chip size. Also, the demand for greater functionality is driving the “design rule” lower, for example, from a 0.35-0.25 micron technology to a 0.18 micron, or a 0.15 micron technology, or even lower.
A portion of a conventional flash memory cell that comprises a flash memory IC is illustrated in FIG.
1
. In referring to
FIG. 1
, a portion of a conventional flash memory cell fabrication process is described.
FIG. 1
illustrates a cross-sectional view of the single flash memory cell
10
that is comprised of a conventional substrate
20
. However, the respective source and drain regions are not shown. A tunnel oxide (“T
ox
”) layer
30
is formed over the upper substrate portion
22
, over which is formed a first polysilicon layer
40
. Polysilicon layer
40
may be patterned, for example, by masking and etching. Next, an interpoly dielectric layer
50
, e.g., Oxide Nitride Oxide (“ONO”), is formed over the first polysilicon layer
40
. Then, a second polysilicon layer
60
is formed upon the interpoly dielectric layer
50
. The conventional silicide layer is omitted for clarity.
The memory device illustrated in
FIG. 1
utilizes the first polysilicon layer
40
as a floating gate in order to store a data element. The floating gate is controlled by the second polysilicon layer
60
that functions as a control gate.
Conventional voltages of the stored data element may be on the order of 3.3 volts. However, the voltage that is applied to the control gate, or second polysilicon layer
60
, that controls access to this data element may be on the order of 9 volts. Thus, a conventional charge pump, not shown, may be located on the flash memory IC in order to raise the chip voltage from 3.3 volts to a target voltage of approximately 9 volts.
Charge pumps are relatively large, taking up substantial space on the memory cell and further compromising the reliability of the IC. As design rules continue to decrease, the size of the charge pump becomes an obstacle in chip design. However, the size of the charge pump may be decreased by decreasing the target voltage. The target voltage may be decreased by increasing the gate coupling ratio (“&agr;”) of the memory cell.
The gate coupling ratio (“&agr;”) may be defined as:
&agr;=C
ono
/(C
ono
+C
tox
)
where C
ono
is the capacitance between the first polysilicon layer
40
and the second polysilicon layer
60
, and C
tox
represents the capacitance between the substrate upper portion
22
and the first polysilicon layer
40
.
Accordingly, what is needed is an IC device and a method of fabricating an IC device that allows for an improvement in the gate coupling ratio performance. By increasing the gate coupling ratio performance, the target voltage of the charge pump may be decreased. Thus, the power consumption of the IC may thereby be decreased. This, in turn, may allow for decreasing the size of the charge pump and improving the reliability of the IC device.
Further, by reducing the charge pump size, the device density may be improved, i.e. increased.
One solution is to increase the width of the first polysilicon layer
40
so as to increase the capacitance. However, this also undesirably limits the ability to reduce the cell
10
size and thus impedes device density improvements.
What is needed is a device and method for improving the capacitance between the first polysilicon layer
40
and the second polysilicon layer
60
, while keeping the first polysilicon layer
40
and tunnel oxide layer
30
contact area relatively low.
SUMMARY OF THE INVENTION
Embodiments of the present invention are best understood by examining the detailed description and the appended claims with reference to the drawings. However, a brief summary of embodiments of the present invention follows.
Briefly described, an embodiment of the present invention comprises a device and a method that provides for the improvement of the coupling ratio performance of an integrated circuit device.
This improvement is achieved by increasing an overlap portion between the first and second polysilicon layers, so as to increase the effective coupling ratio between the layers. In an embodiment of the present invention, a relatively tall or large portion of oxide is formed over at least a portion of each of a plurality of shallow trench isolation regions. This oxide is then utilized to provide a larger first polysilicon layer surface area, but without substantially increasing the tunnel oxide layer surface area. Then, a dielectric interlayer is formed upon the surface of the first polysilicon layer, and next, a second polysilicon layer is formed upon the dielectric interlayer. This increased overlap portion thus allows for an increased coupling ratio. Further, the coupling ratio may be tailored by adjusting either or both of the first and second polysilicon layer surface areas without requiring a substantial change in the tunnel oxide layer surface area.
An embodiment of the present invention provides a device and method for improving the coupling ratio. The coupling ratio may be tailored by adjusting either or both the first and second polysilicon area sizes independently of the tunnel oxide area.
This invention may be implemented for a shallow trench isolation structure (“STI”) type device, as well as other devices.
Other arrangements and modifications will be understood by examining the detailed description and the appended claims with reference to the drawings.
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patent: 5643813 (1997-07-01), Acocella et al.
patent: 6130129 (2000-10-01), Chen
patent: 6153494 (2000-11-01), Hsieh et al.
patent: 6171907 (2001-01-01), Tuntasood
patent: 6184085 (2001-02-01), Jeong
patent: 6214667 (2001-04-01), Ding et al.
patent: 6228713 (2001-05-01), Pradeep et al.
S. Aritome et al., A 0.67 um2 Self-Aligned Shallow Trench Isolation Cell (SA-STI-Cell) For 3V-only 256Mbit NAND EEPROMS, IEDM, pp. 61-64, 1994.*
Y.S. Hisamune, A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories, IEDM, pp. 19-22, 1993.
Park Steven K.
Wang Larry Y.
Advanced Micro Devices , Inc.
Eckert, III George C.
Foley & Lardner
Lee Eddie
LandOfFree
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