Flash memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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Details

C365S185170

Reexamination Certificate

active

11299063

ABSTRACT:
A flash memory device comprises a first group of dummy memory cells disposed between source selection transistors, which are coupled to a source selection line, and memory cells coupled to a first wordline. The flash memory device further comprises a second group of dummy memory cells disposed between drain selection transistors, which are coupled to a drain selection line, and memory cells coupled to the last wordline. The flash memory device is configured to prevent program disturbance in deselected cell strings and degradation of programming/erasing speeds in a selected cell string.

REFERENCES:
patent: 5524094 (1996-06-01), Nobukata et al.
patent: 7079437 (2006-07-01), Hazama et al.
patent: 2004/0169206 (2004-09-01), Kim et al.
patent: 2000-111573 (2000-04-01), None
patent: 2001-006377 (2001-01-01), None
patent: 2001-006377 (2001-12-01), None
patent: 2004-127346 (2004-04-01), None
patent: 10-2000-0042829 (2000-07-01), None

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