Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-07
2004-06-08
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S319000
Reexamination Certificate
active
06747310
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention pertains generally to semiconductor memory devices and, more particularly, to nonvolatile memory and the manufacture thereof.
2. Related Art
Nonvolatile memory is currently available in several forms, including electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM.
U.S. Pat. Nos. 6,091,104 and 6,291,297 show a split-gate memory cell of relatively small size, efficient erase performance, and relatively programming current requirements. The small size is obtained through self-alignment of the select, control and floating gates, and the efficiency in erasing is provided by the use of Fowler-Nordheim tunneling from a sharply rounded side edge of the floating gate to the select gate. The programming current is kept small by the use of mid-channel hot carrier injection from the off-gate channel region between the select gate and the floating gate to the sharply curved side edge of the floating gate.
A memory cell of this type is illustrated in
FIG. 1
as having a floating gate
16
, a control gate
17
, and select gate
18
, all of which are fabricated of polysilicon. The control gate is stacked above the floating gate, and the select gate is positioned to the side of the stacked gates. With the three polysilicon gates which are formed in a triple polysilicon fabrication process, this type of cell is sometimes referred to as a 3P self-aligned split gate cell.
In the programming mode, the control gate is biased at a voltage of about 10 volts, the select gate is biased at about −2 volts, and the source
19
is biased at about −6 volts. The strong electric field thus established across the mid-channel gate oxide
21
between select gate
18
and floating gate
16
causes electrons to be accelerated and injected into the floating gate, as indicated by arrow
22
.
In the erase mode, a negative voltage of about −10 volts is applied to the control gate, and a positive voltage of about 6 volts is applied to the select gate. In this mode, the electric field across the inter-poly oxide
23
between the select gate and the rounded side wall
24
of the floating gate initiates Fowler-Nordheim tunneling, with electrons flowing from the floating gate to the select gate, as indicated by arrow
While the 3P self-aligned split gate cell structure and the unique programming and erase techniques employed with it permit a smaller cell size than the widely used ETOX structure, as cell sizes decrease into the range of hundreds of nanometers, it is limited by the need to remove polysilicon from the source region and in the narrow, steep valleys between adjacent control and floating gate stacks.
OBJECTS AND SUMMARY OF THE INVENTION
It is in general an object of the invention to provide a new and improved flash memory cell and fabrication process.
Another object of the invention is to provide a memory cell and process of the above character which overcome the limitations and disadvantages of the prior art.
Another object of the invention is to provide a memory cell and process of the above character in which the memory cell is very small in size and provides significantly enhanced programming and erase performance.
These and other objects are achieved in accordance with the invention by providing a flash memory and process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source diffusion in a substrate, an erase gate is formed directly above the source diffusion and between the stacked gates, select gates are formed on the sides of the stacked gates opposite the erase gate, programming paths extend from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extend from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate. In some embodiments, the source regions are connected electrically to the erase gates, and in others the floating gates project laterally beyond the control gates on one or both sides of the control gates. These memory cells are very small in size and provide substantially better programming and erase performance than memory cells of the prior art.
REFERENCES:
patent: 5874759 (1999-02-01), Park
patent: 6091104 (2000-07-01), Chen
patent: 6291297 (2001-09-01), Chen
patent: 6476440 (2002-11-01), Shin
Chen Chiou-Feng
Fan Der-Tsyr
Tuntasood Prateep
Actrans System Inc.
Ho Tu-Tu
Nelms David
Wright Edward S.
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