Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-02-04
2003-11-18
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S384000
Reexamination Certificate
active
06649968
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to FLASH memory and methods of forming FLASH memory.
BACKGROUND OF THE INVENTION
Memory is but one type of integrated circuitry. Some memory circuitry allows for both on-demand data storage and data retrieval. For example, memories which allow both writing and reading, and whose memory cells can be accessed in a random order independent of physical location, are referred to as random-access memories (RAM). Read-only memories (ROMs) are those in which only the read operation can be performed rapidly. Entering data into a read-only memory is typically referred to as programming, and the operation is considerably slower than the writing operation utilized in random-access memory. With random-access memory, information is typically stored with respect to each memory cell either through charging of a capacitor or the setting of a state of a bi-stable flip-flop circuit. With either, the stored information is destroyed when power is interrupted. Read-only memories are typically non-volatile, with the data being entered during manufacturing or subsequently during programming.
Some read-only memory devices can be erased as well as written to by a programmer. Erasable read-only memory typically depends on the long-term retention of electronic charge as the information storage mechanism. The charge is typically stored on a floating semiconductive gate, such as polysilicon. One type of read-only memory comprises FLASH memory. Such memory can be selectively erased rapidly through the use of an electrical erase signal.
A FLASH memory cell typically comprises a single floating gate transistor. For multiple storage cells, such as used in large semiconductor memories, the storage cells of the memory are arranged in an array consisting of rows and columns. The rows are typically considered as comprising individual conductive gate lines formed as a series of spaced floating gates received along a single conductive line. Source and drain regions of the cells are formed relative to active area of a semiconductor substrate, with the active areas being generally formed in lines running substantially perpendicular to the lines of floating gates. The sources and drains are formed on opposing sides of the lines of floating gates within the active area with respect to each floating gate of the array. Thus, lines (rows) of programmable transistors are formed.
Electrical connections are made with respect to each drain to enable separate accessing of each memory cell. Such interconnections are arranged in lines comprising the columns of the array. The sources in FLASH memory, however, are typically all interconnected and provided at one potential, for example ground, throughout the array. Accordingly, the source regions along a given line of floating gates are typically all provided to interconnect within the substrate in a line running parallel and immediately adjacent the line of floating gates. These regions of continuously running source area are interconnected outside of the array, and strapped to a suitable connection for providing the desired potential relative to all the sources within the array. Accordingly, prior art techniques have been utilized to form a line of continuously running implanted source material within the semiconductor substrate and running parallel with the floating gate word lines.
In a principal technique of achieving the same, the substrate has first been fabricated to form field oxide regions by LOCOS. The fabrication forms alternating strips of active area and LOCOS field oxide running substantially perpendicular to the floating gate word lines which will be subsequently formed. Thus running immediately adjacent and parallel with the respective word lines will be an alternating series of LOCOS isolation regions and active area regions on both the source and drain sides of a respective line of floating gates. After forming the lines of floating gates and to provide a continuous line of essentially interconnected source regions, the substrate is masked to form an exposed area on the source side of the respective lines of floating gates. The LOCOS oxide is then selectively etched relative to the underlying substrate. This leaves a series of spaced trenches along the lines of floating gates the result of removal of oxide from the previously oxidized substrate which formed the LOCOS regions.
Non-recessed LOCOS in fabrication of FLASH memory in this manner is typically very shallow relative to the semiconductor substrate (i.e., less than 1500 Angstroms deep). This leaves a gradual, almost sinusoidal, undulating surface of exposed semiconductor substrate running in lines substantially parallel and immediately adjacent the lines of floating gates on the desired source side. With the gently sloping sidewalls of the trenches or recesses left by the LOCOS oxide removal, one or more source ion implant steps are conducted through the mask openings of the remaining photoresist layer. The result is formation of a continuously and conductively doped source line within the semiconductor substrate immediately adjacent the line of floating gates.
Circuitry fabrication and isolation of adjacent circuitry within a semiconductor substrate can also be achieved with a trench isolation that is different from LOCOS. For example, trenches can initially be etched within a semiconductor substrate and subsequently filled with an insulating material, such as high density plasma deposited oxide. Such trenches can and are sometimes made considerably deeper relative to the outer substrate surface as compared to the oxidation depth of LOCOS. Accordingly, the etching typically produces elongated, deeper and straighter sidewalls than LOCOS. When utilized in a FLASH memory fabrication process, such as described above, the result will be fabrication of discrete and disjointed source regions below the base of the trenches and in the plateaus or mesa areas of the active area therebetween. Thus, continuous source lines may not be formed in all instances.
The invention was motivated in overcoming this particular problem in FLASH memory cell fabrication associated with shallow trench and refill isolation. The artisan will, however, appreciate applicability of the invention in other areas, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.
SUMMARY OF INVENTION
The invention comprises FLASH memory and methods of forming flash memory. In one implementation, a line of floating gates is formed over a semiconductor substrate. The semiconductor substrate is etched to form a series of spaced trenches therein in a line adjacent and along at least a portion of the line of floating gates. At least one conductivity enhancing impurity implant is conducted into the semiconductor substrate at an angle away from normal to a general orientation of the semiconductor substrate to implant at least along sidewalls of the trenches and between the trenches, and a continuous line of source active area is formed within the semiconductor substrate along at least a portion of the line of floating gates.
In another implementation, a line of floating gates is formed over a semiconductor substrate. An alternating series of trench isolation regions and active area regions are provided in the semiconductor substrate in a line adjacent and along at least a portion of the line of floating gates. The series of active areas define discrete transistor source areas separated by trench isolation regions. A conductive line is formed over the discrete transistor source areas and trench isolation regions separating same adjacent and along at least a portion of the line of floating gates. The conductive line electrically interconnects the discrete transistor source areas. Source forming conductivity enhancing impurity is provided into the discrete transistor source areas.
Other implementations are contemplated.
REFERENCES:
patent: 4698900 (1987-10-01), Esquivel
patent: 5153143 (1992-10-01), Schlais et al.
patent: 5270240 (
Micro)n Technology, Inc.
Nguyen Tuan H.
Wells St. John P.S.
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