Flash memory cell with vertical channels, and source/drain bus l

Details Flash memory cell with vertical channels, and source/drain bus l Flash memory cell with vertical channels, and source/drain bus l

1999-09-27

2000-05-23

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257321, H01L 29788

Patent

active

060668741

ABSTRACT:
A vertical memory device on a silicon semiconductor substrate comprises a floating gate trench in the substrate. in the array, the trench. The walls of the floating gate trench were doped with a threshold implant through the trench surfaces. There is a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. There is a floating gate electrode in the trench on the outer surfaces of the tunnel oxide layer. There are source/drain regions in the substrate self-aligned with the floating gate electrode. The source line and a drain line form above the source region and the drain region respectively. An interelectrode dielectric layer overlies the top surface of the floating gate electrode, and the source line and the drain line, and there is a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

REFERENCES:
patent: 5451538 (1995-09-01), Fitch et al.
patent: 5467305 (1995-11-01), Bertin et al.
patent: 5495441 (1996-02-01), Hong
patent: 5587949 (1996-12-01), Bergemont et al.
patent: 5595927 (1997-01-01), Chen et al.
patent: 5751038 (1998-05-01), Mukherjee
patent: 6002151 (1999-12-01), Lin et al.

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