Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-27
2001-11-06
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000
Reexamination Certificate
active
06313498
ABSTRACT:
This invention pertains generally to semiconductor devices and, more particularly, to a nonvolatile memory device and fabrication process.
Electrically programmable read only memory (EPROM) has been widely used as nonvolatile memory which can keep data unchanged even though the power is turned off. However, EPROM devices have a major disadvantage in that they have to be exposed to Ultra-Violet (UV) light for about 20 minutes for data erasure. This is very inconvenient because an EPROM device has to be unplugged from its socket and moved to the UV light source when the data needs to be changed.
Electrically erasable programmable read only memory (EEPROM) overcomes this problem and permits data to be erased electrically in a much shorter period of time, typically less than 2 seconds. However, it still has a disadvantage in that the data must be erased on a byte-by-byte basis.
Flash EEPROM is similar to EEPROM in that data is erased electrically and relatively quickly. However, with flash EEPROM, the data is erased in blocks which typically range in size from 128 to 64K bytes per block, rather than on a byte-by-byte basis.
In general, there are two basic types of nonvolatile memory cell structures: stack-gate and split-gate. The stack-gate memory cell usually has a floating gate and a control gate, with the control gate being positioned directly above the floating gate. In a split-gate cell the control gate is still positioned above the floating gate, but it is offset laterally from it. The fabrication process for a stack-gate cell is generally simpler than that for a split-gate cell. However, a stack-gate cell has an over-erase problem which a split-gate cell does not have. This problem is commonly addressed by maintaining the threshold voltage of the cell in a range of about 0.5-2.0 volts after an erase cycle, which adds complexity to the circuit design.
Although a split-gate memory cell has no over erase problem, it generally includes an additional gate known as a select gate. Such cells are typically fabricated in double-poly or triple-poly processes which involve relatively complex processing steps. In addition, split-gate cells are generally larger than stack-gate cells. Nevertheless, because of the relatively simple circuit design which is possible when there is no over-erase problem, split-gate cells are used widely, particularly in embedded nonvolatile memory applications.
FIG. 1
illustrates split-gate memory cell having a control gate
16
which only partially overlies the floating gate
17
. In the programming mode, the source
18
is biased at a relatively high voltage of about 12 volts, the control gate is biased at about 3 volts, and the drain
19
is grounded. With this biasing condition, most of source-to-drain voltage is applied across the mid-channel region
21
between the control gate and the floating gate, creating a strong electric field in that region. As the electrons flow from the drain to the source, they are accelerated by the electric field in the mid-channel region and become heated. The floating gate is coupled to the source node and is therefore at a higher voltage level than the mid-channel region, which produces a second electric field which extends vertically. That field accelerates some of the hot electrons in the mid-channel region so that they exceed the energy barrier of the oxide layer
22
(about 3.1 eV) and are injected into floating gate. This technique is described in greater detail in U.S. Pat. Nos. 4,794,565, 5,029,130 and 5,455,792.
In the erase mode, the control gate is biased at a high voltage of about 15 volts, the source and drain nodes are biased at 0 volts, and the drain node is open. A high voltage is now formed across the inter-poly dielectric
23
between the floating gate and the control gate. The edge
17
a
of the floating gate functions as a cathode electrode where Fowler-Nordheim tunneling takes place, and electrons flow from the floating gate to control gate, leaving the floating gate charged with positive ions.
FIG. 2
illustrates a split-gate memory cell in which the control gate
16
completely overlies the floating gate
17
. In this device, the floating gate is coupled more closely to the control gate than to the source region, and the control gate is used for coupling voltages to the floating gate. In the programming mode, hot carrier injection is once again utilized for injecting electrons into the floating gate, with the control gate being biased at about 12 volts, drain
19
biased at 0 volts, and source
18
biased at about 7 volts. When electrons flow from the drain to the source, they are accelerated by high electric field across the channel region
21
, and some of them become heated near the source junction. Some of the hot electrons can exceed the oxide barrier height and are injected into floating gate.
In the erase mode, Fowler-Nordheim tunneling is utilized to force electrons to tunnel from the floating gate to the overlapped portion of the source region
18
a
under the floating gate. During erase operations, a high electric field (greater than 10 mV/cm) is established across the thin oxide layer
22
by applying about 15 volts to the source node, 0 volts to the control gate, letting the drain node float. As a result, most of the voltage difference between the source and the control gate is applied across the thin oxide, triggering Fowler-Nordheim tunneling and forcing electrons to tunnel from the floating gate to the overlapped portion of the source region. This technique is also utilized in stack-gate cells, and is described in greater detail in U.S. Pat. Nos. 5,402,371, 5,284,784 and 5,445,792.
U.S. Pat. No. 5,029,130 shows a split-gate memory cell in which a sharp, upwardly curved edge is formed on the floating gate to create a well-defined charge injection edge in order to provide a high probability of electron tunneling. By adding a third polycrystalline silicon layer as an erase layer which crosses over, or overlies, the floating gate and the control gate, an erase path can be formed between the side wall of floating gate and the erase layer. This technique is disclosed in U.S. Pat. Nos. 5,847,996 and 5,643,812.
Fowler-Nordheim tunneling has also been utilized with both split-gate cells and stack-gate cells to form a negative charge on the floating gate in the programming mode, and U.S. Pat. No. 5,402,371 shows one example of a device in which electrons are forced to tunnel into the floating gate from the channel region beneath it.
It is in general an object of the invention to provide a new and improved memory cell and process for fabricating the same.
Another object of the invention is to provide a memory cell and process of the above character which overcome the limitations and disadvantages of the prior art.
These and other objects are achieved in accordance with the invention by providing a nonvolatile memory cell and process in which a thin floating gate is formed with a rounded lateral edge and a thickness on the order of 100-1000 Å over a gate oxide in an active area on a silicon substrate. A tunnel oxide is formed adjacent to the rounded edge of the floating gate, and a control gate is formed with a lower portion next to the tunnel oxide and an upper portion overlying the floating gate. In some embodiments, the upper portion of the control gate completely overlies the floating gate, and in others it only partially overlies it.
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Actrans System Inc.
Crane Sara
Flehr Hohbach Test Albritton & Herbert LLP
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