Flash memory cell using poly to poly tunneling for erase

Details Flash memory cell using poly to poly tunneling for erase Flash memory cell using poly to poly tunneling for erase

1998-09-18

2000-09-05

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257317, 257239, 257367, 257321, 257249, 257775, H01L 29788, H01L 2976, H01L 27148

Patent

active

061147230

ABSTRACT:
An improved split gate flash memory cell is disclosed whose floating gate is formed to have a reentrant angle such that its width increases with increased distance from the substrate so as to minimize the possibility of defects in the poly oxide layer overlaying the floating gate. The split gate flash memory is fabricated using a process comprising the steps of: (a) forming a floating gate with an overlaying poly oxide layer on a substrate, wherein the floating gate is etched to have a reentrant angle such that its width generally increases with a distance from the substrate; (b) forming a CVD nitride spacer on the floating gate using a CVD nitride deposition, then anisotropic etching the CVD nitride to form a nitride spacer adjacent to the floating gate; (c) forming a control gate on the floating gate wherein the control gate and the floating gate are separated by the poly oxide and the nitride spacer; and (d) forming a source and drain in the substrate using a source and drain implantation.

REFERENCES:
patent: 5267194 (1993-11-01), Jang
patent: 5494838 (1996-02-01), Chang et al.
patent: 5554553 (1996-09-01), Harari
patent: 5783473 (1998-07-01), Sung

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