Flash memory cell transistor and method for fabricating the...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S369000, C257S371000, C257S411000, C257SE29309

Reexamination Certificate

active

11430118

ABSTRACT:
A flash memory cell transistor and a method for fabricating the same compensates a work function difference of a pMOS and a nMOS with a triple gate insulating film by using electron density trapped in a pMOS gate insulating film. The flash memory cell transistor comprises a p-well region and a n-well region. The nMOS region comprises a nMOS channel ion-implantation region on the p-well region, a second gate oxide film on the nMOS channel ion-implantation region and a first n+ polysilicon gate electrode on the second gate oxide film. The pMOS region comprises a pMOS channel ion-implantation region on the n-well region, a first gate oxide film, an insulating film having an electron trap and the second gate oxide film which are sequentially formed on the pMOS channel ion-implantation region, and a second n+ polysilicon gate electrode on the second gate oxide film.

REFERENCES:
patent: 5650346 (1997-07-01), Pan
patent: 6201275 (2001-03-01), Kawasaki
patent: 6762453 (2004-07-01), Simacek et al.
patent: 2004/0180501 (2004-09-01), Liu
patent: 2000-49351 (2000-02-01), None
patent: 2002-373944 (2002-12-01), None
patent: 1020050070805 (2005-07-01), None
Tomoko Ogura et al., “Embedded Twin MONOS Flash Memories with 4ns and 15ns Fast Access Times”, Symposium on VLSI Circuits Digest of Technical Papers, 2003, pp. 207-210.

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