Flash memory cell structure having a high gate-coupling coeffici

Details Flash memory cell structure having a high gate-coupling coeffici Flash memory cell structure having a high gate-coupling coeffici

1997-11-12

1998-12-22

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 438258, H01L 29792

Patent

active

058523138

ABSTRACT:
A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.

REFERENCES:
patent: 4642673 (1987-02-01), Miyamoto et al.
patent: 5084745 (1992-01-01), Iizuka
patent: 5256584 (1993-10-01), Hartmann
patent: 5686749 (1997-11-01), Matsuo

Affiliated with

Also associated with

Rating

Flash memory cell structure having a high gate-coupling coeffici does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flash memory cell structure having a high gate-coupling coeffici, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory cell structure having a high gate-coupling coeffici will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2050423