Flash memory cell having reduced leakage current

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S317000

Reexamination Certificate

active

06897518

ABSTRACT:
A flash memory cell of the present invention comprises a floating gate, having a charge trapping region and a fin region. A source region and a drain region is formed proximate the floating gate. A control gate is formed above the charge trapping region of the floating gate. The fin region advantageously reduces leakage current, thereby allowing further scaling of the cell.

REFERENCES:
patent: 6574143 (2003-06-01), Nakazato
patent: 6649969 (2003-11-01), Tsuji et al.
patent: 6768165 (2004-07-01), Eitan
patent: 6772992 (2004-08-01), Lombardo et al.

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