Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-01
2002-05-07
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C365S185180
Reexamination Certificate
active
06384447
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to nonvolatile memories, and more specifically to flash electrically erasable programmable memory (EEPROM) devices.
BACKGROUND OF THE INVENTION
The standard programming method, hot channel electron injection, for a flash EEPROM cell requires a cell current on the order of 200-500 micro-amperes. A high cell current is required due to the poor efficiency of the injection mechanism and makes simultaneous programming of a large number of cells in a flash memory array impractical. The unmet need for fast and controllable programming of a flash cell using a low current has long been recognized by many workers in the field.
Yeh, in U.S. Pat. No. 5,029,130, describes a method for high efficiency programming using source-side hot electron injection with a cell current of about 1 micro-ampere. Yeh's method allows simultaneous programming, in a time of between 0.1 milliseconds and 10 milliseconds, of all cells on a row of a memory array to an arbitrary pattern (page write). However, a larger cell size is required to accommodate source-side injection, and the larger cell size increases the complexity of the fabrication process over that which is required in the fabrication of the standard flash EEPROM.
Haddad, in U.S. Pat. No. 5,491,657, describes a programming method using the band-to-band generated current of the drain-to-substrate junction. In general, Haddad's method applies to a cell with a structure similar to the standard flash EEPROM. However, Haddad's cell array is placed inside a triple well (P well surrounded by N well). Haddad also describes programming a cell in between 1 and 100 milliseconds with a cell current of below 1 micro-ampere. This allows simultaneous programming of a plurality of cells in a memory array. However, since Haddadt's method requires different gate voltage conditions for the 0 state versus the 1 state, programming of all cells on a row of the memory array to an arbitrary pattern (page write) is not possible. In addition, in a selective data write operation, the band-to-band tunneling process generates both electrons and holes that could be injected with high efficiency into the floating gate, which would disturb the data stored at unselected locations (on selected column and unselected rows) in the memory array. This makes the method inapplicable to the user-mode write function found in a standard device, and useful only in test modes for simultaneous writing of specialized symmetrical patterns of data to an entire memory array or block.
Chen describes a cell structure and biasing method that may allow the band-to-band generated current in a flash memory cell to be selectively turned on and off at specific locations in a memory array, thus making this low current programming mechanism applicable to the standard user-mode write functions. I. C. Chen et al.,
Band
-
to
-
band tunneling induced substrate hot
-
electron
(
BISHE
)
injection: A new programming mechanism for nonvolatile memory devices
, 1989 International Electron Devices Meeting Technical Digest—International Electron Devices Meeting, 263-266 (1989). However, the cell structure described by Chen uses a large area, a relatively thick programming dielectric (SiO
2
) layer, and a large bias voltage, which makes the cell structure unsuitable for use as a replacement for the flash EEPROM devices in use today. Chen's description is limited to the physical programming mechanism, and does not describe the operation of the proposed cell in performing other functions, such as electrical erase, read
1
(erase state) and a particular type of write disturb present in such a memory array, which will be described below. Proper operation in all these functions is required in a flash EEPROM device and will be demonstrated for the cell proposed in this invention.
Chen also describes a design using a programming dielectric of about 100 Å that was rejected due to the potential write disturb by Fowler-Nordheim injection in unselected cells (columns) along the same row with the cell to be programmed. According to the bias scheme proposed by Chen, programming is achieved by applying 4 volts on the drain of the cells to be programmed, 0 volts on the drain of the cells to remain erased, and floating the common source. Chen apparently ignored the fact that, as the drain diffusion is raised to 4 volts and the floating gate coupled to about 10 volts or more in the cells to be programmed, the floating source could also rise to an uncontrolled voltage level. For the symmetrical source/drain structure described by Chen, the source junction could generate as much band-to-band current in any cell as the drain junction. This band-to-band current generated in the source junction together with the current required to charge the source junction capacitance represents an undesirable power drain on the supply (pump) used to provide current for the programming function. Furthermore, if the source potential rises to about 3 volts or more, band-to-band current induced electron injection, which is the same mechanism used to program the selected cells, may cause disturb in the cells intended to remain erased on the selected row.
For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
The above mentioned problems with flash memory cells and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
A flash memory cell comprises a control gate, a drain region, a source region, and a channel region formed in a common substrate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and about six volts across a shallow deep-depletion region created near the drain region. The voltage drop is induced by applying a first voltage to the control gate, a second voltage to the drain region, and a third voltage to the source region.
REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 5321286 (1994-06-01), Koyama et al.
patent: 5486480 (1996-01-01), Chen
patent: 5487033 (1996-01-01), Keeney et al.
patent: 5491657 (1996-02-01), Haddad et al.
patent: 5553020 (1996-09-01), Keeney et al.
patent: 5574685 (1996-11-01), Hsu
patent: 5739569 (1998-04-01), Chen
patent: 5783457 (1998-07-01), Hsu
patent: 5986941 (1999-11-01), Pang et al.
patent: 6026017 (2000-02-01), Wong et al.
patent: 6088263 (2000-07-01), Liu et al.
patent: 6111286 (2000-08-01), Chi et al.
patent: 6137727 (2000-10-01), Cleveland
patent: 6172397 (2001-01-01), Oonakado et al.
patent: 6274901 (2001-08-01), Odake et al.
patent: 6284603 (2001-09-01), Ho Simon et al.
Oda et al., New Buried Channel Flash Memory Cell with Symmetrical Source/Drain Structure for 64Mbit or beyond, IEEE Symp. on VLSI Tech, 1994, pp. 69-70.*
Bude, J.D., et al., “EEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Writing”,International Electron Devices Meeting, pp. 989-991, (1998).
Chen, I.C., et al., “Band-to-Band Tunneling Induced Substrate Hot-Electron (BBISHE) Injection: A New Programming Mechanism for Nonvolatile Memory Devices”,International Electron Devices Meeting, pp. 263-266, (1989).
Kencke, D.L., et al., “The Origin of Secondary Electron Gate Current: A Muliple-stage Monte Carlo Study for Scaled, Low-power Flash Memory”,International Electron Devices Meeting, pp. 889-892, (1998).
Kim, D.M., et al., “Stacked Gate Mid-Channel Injection Flash EEPROM Cell ---Part I: Programming Speed and Efficiency Versus Device Structure”,IEEE Transactions on Electron Devices, 45 (8), pp. 1696-1702, (Aug. 1998).
Chen Chun
Mihnea Andrei
Rudeck Paul J.
Lebentritt Michael S.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Wilson Christian D.
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