Flash memory cell, flash memory cell array and manufacturing...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S316000, C257S321000, C257S324000, C257S326000, C438S201000, C438S257000, C438S258000

Reexamination Certificate

active

06911690

ABSTRACT:
A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

REFERENCES:
patent: 5677216 (1997-10-01), Tseng
patent: 6373095 (2002-04-01), Bracchitta et al.
patent: 6720610 (2004-04-01), Iguchi et al.
patent: 6770920 (2004-08-01), Yoo et al.
patent: 2003/0127684 (2003-07-01), Yoo et al.
patent: 2004/0185615 (2004-09-01), Ding

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