Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-02-27
2007-02-27
Huynh, Andy (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S686000, C438S666000, C438S299000, C438S257000, C438S303000, C438S305000
Reexamination Certificate
active
11160743
ABSTRACT:
A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region. The p-type doped region passes through the junction between the drain region and the p-type pocket doped region but is separated from the spacer by a distance. The contact plug is set up over the drain region and is electrically connected to the p-type doped region.
REFERENCES:
patent: 5899722 (1999-05-01), Huang
patent: 6136649 (2000-10-01), Hui et al.
patent: 6194784 (2001-02-01), Parat et al.
patent: 2003/0068859 (2003-04-01), Leung et al.
Du Chien-Chih
Hsue Chen-Chiu
Sung Da
Wang Leo
Huynh Andy
Jianq Chyun IP Office
Nguyen Tram H.
Powerchip Semiconductor Corp.
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