Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2002-04-23
2003-06-24
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Addressing
Multiple port access
C365S230030, C365S189050, C365S214000, C365S230060, C365S189040
Reexamination Certificate
active
06584034
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor flash memory, and more particularly to multiple simultaneous read and write operations on a flash memory.
2. Description of the Related Art
Non-volatile memories, especially flash memories, are widely used in various applications such as computers, hand-held devices, communication devices and consumer products. Since a flash memory is nonvolatile and permits an on system electronic programmability, the flash memory is suitable to store the program code and data code for microprocessors. Flash memory has become widely used in storage for voice data and video data; however, flash memory has a significant drawback in that it requires a relatively long time to process a write operation. It typically takes several milliseconds to several seconds to write data. During this time period, the data stored in the memory cannot be read causing inconvenience of operation. Therefore, a simultaneous operating flash memory is used to fulfill this requirement. The simultaneous operating flash memory allows data to be read out when the memory is performing the write operation. In conventional simultaneous operating flash memories there are two individual banks having fixed memory density. Each bank can independently perform read and write operations, and therefore, the data stored in one bank can be read while the other bank is performing the write operation. There are two significant drawbacks to this prior art configuration: 1) It lacks of flexibility for the memory density of each bank. The density of each bank is determined in the design step, and cannot be altered after manufacturing. 2) The bank size is large. When new data is written into one bank, the other data stored in the bank being written cannot be read.
In order to overcome these problems, some of the prior art increases the flexibility of the array partition and make smaller array partitions creating a different set of drawbacks. To better understand the basic operations of flash memories the read operation is defined as reading stored data from selected memory cells, and the write operation is defined as all the operations involved in changing the data stored in selected cells. A write operation generally includes several operations: 1) An erase operation that is used to remove the previous old data from selected memory cells. 2) A program operation that is used to store new data into selected memory cells. 3) A preprogram operation that is used to increase the Vt of the selected cells before the erase operation. 4) A correct, repair, soft program, or converge operation that is used to make the Vt of over erased cells to be in an allowable range. 5) A de-trap operation that is used to remove the hot hole trapped inside the tunnel oxide after the erase or program operations. All of these operations are a part of a write operation. The required operations vary for different flash memories. Some flash memories require fewer operations while-others require all of the operations. Also different types of flash memory cells, technologies, and array architectures, generally require different bias conditions and operation timing.
In U.S. Pat. No. 6,088,264 (Hazen et al.) a method is directed to divide flash memory array into several partitions as shown in FIG.
1
A. Each array partition
210
has its own X decoder
220
and y decoder
230
. This makes each array partition into a mini array. Each array partition can perform a write or read operation independently and simultaneously with the other partitions. This approach is the extension of the conventional simultaneous flash memories, except that it utilizes more than two banks. Because more than two partitions are used, a smaller partition size can be achieved having more flexible operations. However, the prior art of U.S. Pat. No. 6,088,264 has several drawbacks: 1) A separate y decoder for each array partition which causes an area penalty. 2) The array partition is fixed in size. 3) The array partition is large. 4) The common data lines connected to the y decoder of each array partition have large parasitic load capacitance that can cause significant read delay for the sense amplifiers.
To overcome the problems associated to the prior art of
FIG. 1A
, U.S. Pat. No. 6,033,955 (Kuo et al.) discloses another approach shown in
FIG. 1B
, which is directed to change the size of the partition. The prior art of
FIG. 1B
divides the flash memory array
20
into two partitions, called upper bank
22
and lower bank
21
. Each bank has its own y decoders
32
and
34
, one located on the top of the array and the other one located on the bottom of the array. The prior art of
FIG. 1B
is directed toward using a metal bit line option during the manufacturing to alter the boundary between the upper bank and the lower bank. This allows the size of the two partitions to be altered, while the total size of the two partitions keep constant. However, there are several drawbacks to the prior art of FIG.
1
B: 1) An array can be only partitioned into two partitions. 2) The flexible boundary of the two array partitions has to be decided in a manufacturing step, and cannot be altered after manufacturing. 3) Although one array partition can be small size, the other one will become very large size.
In U.S. Pat. No. 6,240,040 B1 (Akaogi et al.) an architecture is directed to address buffering and decoding for a multiple bank simultaneous operating flash memory. U.S. Pat. No. 6,052,327 (Reddy et al.) is directed to a dual port memory array for a logic device where data words may be read and written simultaneously. In U.S. Pat. No. 5,867,430 (Chen et al.) a flash memory device is directed to multiple banks each with a decoder and a plurality of sectors to allow simultaneous read and write operations. U.S. Pat. No. 5,847,998 is directed to a nonvolatile memory array that has a plurality of sectors with independent read and write paths which permit reading from one sector while writing to a second sector. U.S. Pat. No. 5,841,696 is directed to a nonvolatile memory which allows simultaneous read and write operations using time multiplexing of an x-decode path between read and write operations.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a flash memory with multiple simultaneous operations that overcomes the drawbacks of the simultaneous operating flash memories of the prior art.
Another objective of the present invention is to provide a new approach that can fully produce a simultaneously read and write operation of a non-volatile memory.
Still another objective of the present invention is to provide smaller array partition.
A further objective of the present invention is to provide a flexible array partition.
Still a further objective of the present invention is to provide an array that contains at least two or more sectors where each sector has an associated sector decoder.
Also a further objective of the present invention is to provide main bit lines that are divided into at least two or more groups, where each group of bit lines can perform different operations separately.
Also a still further objective of the present invention is to provide a sector decoder that has at least two output ports to connect the main bit line groups to sub bit lines.
The present invention is related to the array architecture of non-volatile memories, especially flash memories. Its application is broad and is not limited in any special type of flash memory. The basic concept of the present invention can be utilized for any type of array structure, comprising such structures as NOR, NAND, AND, OR, Dual-String, and DINOR. Moreover, the basic concept of the present invention can be utilized for any type of memory cells, comprising such cells as ETOX, FLOTOX, EPROM, EEPROM, Split-gate and PMOS. Three embodiments of array architectures will be demonstrated that use typical NOR, AND, and NAND array structures. Although, the present invention can utilize a 2
M
sector decoder, the demonstration of the p
Hsu Fu-Chang
Lee Peter W.
Tsao Hsing-Ya
Aplus Flash Technology Inc.
Ho Hoai
Pham Ly Duy
LandOfFree
Flash memory array structure suitable for multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flash memory array structure suitable for multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory array structure suitable for multiple... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3124218