Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1997-03-25
2002-04-30
Yoo, Do Hyun (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S104000
Reexamination Certificate
active
06381670
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a non-volatile memory, more particularly to a flash memory which eliminates pre-programming and repairing by applying a world line (WL) voltage lower than the minimum threshold voltage to shut off all cells including over-erased cells, and provides erasing and programming operations with adjustable bias conditions in accordance with the threshold voltage of the cell to improve the performance.
BACKGROUND OF THE INVENTION
Flash memories are used for their property of data non-volatility. Two kinds of flash memory are commonly available. One is EPROM type flash and the other is EEPROM type flash. These two types of flash are categorized by their data erase/program mechanism. The data of a memory cell depend on the number of electrons in the floating gate of the cell. The more electrons in the floating gate, the higher the threshold voltage (Vt). The cell's data are altered by applying a strong electric field between the floating gate and the source (or drain) region to transfer the electrons. The process of removing the electrons for reducing the Vt is called erase. The process of accumulating electrons for increasing the Vt is called program.
The EPROM type flash uses Fowler-Nordheim (F-N) tunneling effect to erase cells' threshold voltages (Vts) to a low state, and uses channel-hot-electron (CHE) injection to program cells' Vts to a high state. For EEPROM type flash, F-N tunneling is used in both erasing and programming.
The EPROM type flash requires lower programming voltage and, thus, has higher program efficiency than the EEPROM type flash. It also has more market share at present. However, this type of flash erases a block of cells' Vts to low together, so its performance is constrained by an undesirable issue called over-erasure.
Over-erasure results from the block erase scheme and the inherent difference between the erased speed of each cell. Because a large number of cells are erased together, the cells having fast erase speed may be over-erased below 0 V, which is applied to the unselected WLs in verify, repairing, and read mode, while the cells having slow speed are not successfully erased yet. The over-erased cells will conduct leakage current and cause the malfunction of bit line (BL) sense amplifiers.
To overcome this problem, a conventional erase/program operation includes two additional operations, pre-programming and repairing, before and after the erasing, respectively.
FIG. 1
shows the flowchart of a conventional erase/program operation as shown in the prior arts (U.S. Pat. No. 5,359,558) and (U.S. Pat. No. 5,237,535). A number of drawbacks are associated with the conventional erase/program operation. These drawbacks are illustrated as follows.
Firstly, the repairing is performed by applying a low voltage (e.g. 0 V to 0.5 V) to all the world lines (WLs) and a high voltage, such as +5 V to bit line by bit line, to program Vts of all the cells, no matter over-erased or not, back to positive. The experimental result from the prior art (U.S. Pat. No. 5,335,198) showed that, after hundreds of milliseconds to 1 second, the over-erased cell will saturate at approximately 0.6 V. However, this method is difficult for applications with low power supply in that the drain voltage needs to be supplied by an on-chip charge pump. Because the supply current of the charge pump is small, the drain voltage can not be maintained if the number of over-erased cells in a block increases, resulting in failure of the repairing. There are two reasons why the number of the over-erased cells increase. The first one is the shrinkage in the size of cells, which results in process variation increases and thus increases the number of fast cells. The second one is a large block size. The latter problem can be solved by sub-dividing the block into blocks of smaller size for repairing, however, it significantly increases the repairing time.
Secondly, all the cells in the erased block have to be successfully pre-programmed and pre-program verified prior to the erase step to ensure that all the cells have high initial Vt to prevent those cells originally in a erase state from being over-erased. This additional operation drastically increases the erase time, the power consumption, and the stress of the cells that reduces the cells' endurance.
Thirdly, for applications using low voltage power supply, e.g. 3 V, the power supply voltage can not be directly applied and has to be boosted to 5 V in order to read the data.
FIG. 2
shows the Vt distribution of flash memories during the erase/program operation of the prior arts. As shown in
FIG. 2
, Vev is the erase-verify voltage, Vr is the read voltage, Voe is the over-erase voltage, and Vpv is the program-verify voltage. The Vt distribution of the cells as illustrated by B is moved to a distribution as illustrated by C after the pre-program operation. The erase operation changes the Vt distribution from C to A. The repair operation changes the distribution from A to B and the program operation moves the distribution from B to C. The erase-verify voltage Vev, i.e., the upper limit of the erase state, must be high to keep the majority of the erased cell distribution away from being over-erased. Lowering the verify voltage will increase the number of over-erased cells, thus increases the difficulty of repairing.
According to a referenced paper (IEEE Journal of Solid State Circuits, Vol. 27, No. 4, pp. 583, April 1992), the acceptable value of Vev is 3.4 V in the present process. Therefore, for 3 V power supply, the selected WL has to be boosted to approximately 5 V to read data with a WL boost circuit as shown in the prior art (U.S. Pat. No. 5,511,026). The overhead of the boost circuits and power consumption are both greatly increased.
Fourthly, the erase-verification takes a risk of mis-verifying a programmed cell which is a severely over-erased cell or a lightly over-erased cell, as a properly erased cell due to the leakage current.
Fifthly, the repairing is performed on all the erased cells because the over-erased cells can not be distinguished from normally erased cells. Thus the stress of normally erased cells are increased, or moreover, over-repaired to the program state, as reported in U.S. Pat. No. 5,237,535.
Finally, the bias condition for erase/program operations of the prior arts can not provide an optimal performance. With reference to
FIGS. 3A and 3B
for two bias conditions of erase operation and to
FIG. 4
for a bias condition of the CHE program operation as shown in the prior art (U.S. Pat. No. 5,077,691), the bias conditions do not consider the Vt distribution of the cells selected to be erased or programmed. Cells with different Vt values are erased or programmed by the same bias conditions. Besides, the cells' Vt values are changed during the whole erasing and programming operations. The bias conditions are not provided in accordance with true Vt values of the cells but are predetermined. A detailed explanation will be given in the next paragraph to show that the predetermined condition can not provide optimal erase/program performance during the whole erase/program operations because the performance is degraded when cell's Vt change.
SUMMARY OF THE INVENTION
The present invention is designed to overcome the drawbacks mentioned above. The invention presents a novel approach for erasing and programming a flash memory to completely avoid over-erasure induced problems in the prior arts and enhance the erase/program performance by using a novel adjustable bias condition. All the penalties of the conventional operations, including pre-programming and repairing, are eliminated by this invention. In addition, long endurance cycle times and high program efficiency are achieved.
FIG. 5
shows the flowchart of the operation in the invention.
To overcome the over-erasure induced problem, the cells which are defined as being over-erased in the prior arts are shut off by a negative WL voltage, which is lower than the minimum Vt of all the erased c
Fan Wen-Tan
Hsu Fu-Chang
Lee Peter Wung
Tsao Hsing-Ya
Aplus Flash Technology Inc.
Chow Christopher S.
Knowles Billy J.
Yoo Do Hyun
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