Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-07-07
2004-04-13
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S005000, C711S203000, C365S230030, C365S230080
Reexamination Certificate
active
06721843
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of Flash Memory Systems. More particularly, the present invention relates to Flash Memory Systems interfacing with Host Systems.
BACKGROUND OF THE INVENTION
Flash memory technology is an electrically rewritable nonvolatile digital memory medium. Being non-volatile, it does not require a sustained voltage to retain digital data within its memory. A flash memory cell typically stores charge on a floating gate to represent a first logic state in the binary state system, while the lack of stored charge represents a second logic state in the binary state system. Flash memory cells typically support a write operation, a read operation, and an erase operation.
As flash memory technology has advanced, a variety of applications has become possible. In particular, flash memory implementations that emulate the mass storage function of conventional rotating magnetic media, e.g., a hard disk drive or a floppy disk drive, coupled to a host computer system or other host digital system have gained wide acceptance. Hard disk drives and floppy disk drives suffer several deficiencies which are not shared by flash memory technology. First, hard disk drives and floppy disk drives have many moving parts, e.g. an electrical motor, a spindle shaft, a read/write head, and a magnetizable rotating disk. These components give rise to reliability problems and magnify the hard disk drive's and floppy disk drive's susceptibility to failure resulting from the vibration and shock of being dropped or bumped. Secondly, a motor driven disk drive consumes a significant amount of power, substantially shortening the operational time between battery chargings. Finally, accessing data stored in the hard disk drive or the floppy disk is a relatively slow process.
In contrast, a Flash Memory System possesses many advantages over rotating storage disks. The typical Flash Memory System has no moving parts, accounting for the higher reliability of the typical Flash Memory System. In addition, the rugged design of the typical Flash Memory System withstands environmental conditions and physical mishandling that would otherwise be catastrophic to the hard disk drive or the floppy disk drive. Generally, a user can access data stored in the typical Flash Memory System fairly quickly. Finally, the power consumption of the typical Flash Memory System is considerably lower than the hard disk drive's and the floppy disk drive's power consumption.
Because of the market saturation and universal application of rotating media such as hard disk drives, even a superior process or device seeking to capture a share of the market must be compatible with existing software and operating systems. To achieve compatibility with systems configured to store data within legacy rotating mass storage systems, flash memory is typically broken up into a series of data fields capable of storing five hundred twelve bytes of user data and sixteen bytes of overhead data, thereby emulating the size of a data field typically available in commercial hard disks.
FIG. 1
depicts a non-volatile memory array within a flash memory device. A collection of Physical Sectors or Pages
108
, . . .
112
are typically capable of storing of five hundred twelve bytes of user data plus sixteen bytes of overhead data per Page, thereby conforming to the storage capacity of a sector of a typical rotating storage device. A plurality of Physical Pages
108
, . . . ,
112
, typically sixteen or thirty two Pages, comprise a Physical Data Block
102
.
According to the prior art, a Flash Memory System has been comprised of a single memory structure
100
comprising a plurality of Physical Data Blocks
102
, . . .
106
. Each data Physical Data Block
102
, . . . ,
106
is uniquely assigned a Virtual Physical Block Address (VPBA), for identifying and distinguishing a plurality of Physical Data Blocks comprising a Flash Memory System. Usually, each data block
102
, . . . ,
106
is selectively programmable and erasable.
FIG. 2
illustrates one embodiment of flash memory architecture according to the prior art. A Host
215
, such as a computer or digital camera, transmits and receives data to a removable flash memory card
201
. During transmission from the Host to the Flash Memory System, the Host assigns logical block addresses to the data. When retrieving the data, the Host requests data according to the logical block addresses which it previously assigned. The data enters a host interface circuit
203
of the flash memory Controller
202
, by means of a host interface bus
220
, typically comprising parallel bus architecture. The host interface circuit controls the storage of incoming data by means of a RAM Data Buffer
204
. When a predetermined amount of data has been stored within the RAM Data Buffer
204
, the memory interface circuit
205
transmits data through a memory bus
230
to the non-volatile Flash Memory Unit
206
, which was disclosed in greater detail according to FIG.
1
. Typically the data bus
230
is a parallel bus structure. The size of the data buffer
204
is advantageously designed to store an amount of data equal to a multiple of some non volatile memory field, such as a page comprising approximately five hundred twenty eight total bytes of data, depicted in FIG.
1
.
At the present state of technology, a Flash Memory System has a limited number of program cycles before “wearing out.” To ameliorate the problem of wearing-out, a controller discussed in greater detail in
FIG. 2
attempts to cycle through the available memory locations before returning to the first location. By regulating the rate of wear among cells, the controller prevents uneven wear focusing on one area of the Flash Memory System. As a consequence of wear-leveling programs, all the cells within a Flash Memory System will therefore typically wear-out at the same rate. The wear-leveling program therefore reduces the likelihood that the Flash Memory System will experience premature degradation within a localized memory area due to overuse of one area. The entire Flash Memory System therefore remains uniformly reliable through its life. A hard disk drive does not require this wear leveling feature because its storage mechanisms can undergo a practically unlimited number of program/write operations without degrading performance. This contrast results in an operational disparity between the addressing system used within a flash memory, and that used within a hard drive or floppy disk.
In both hard drives and Flash Memory Systems, the physical addresses assigned within a memory typically follow a geometric structure within the memory system. That is, physical addresses will typically increment through successive memory locations. When User Data is received by a memory system, whether Flash Memory or rotating disk, a Host system normally assigns an address to incoming data. In a hard drive, data is typically stored in the sector whose physical address matches the logical address defined by the Host System. If a Host system updates User Data previously defined by a specific logical address, the new data will overwrite the original data at the prescribed address.
In a Flash Memory System, however, as a result of cycling through various areas of a flash memory according to a wear-leveling algorithm, physical areas defined by new physical addresses are continually filled. When a Host system updates User Data defined by a specific logical address and sends it to the Flash Memory System, the wear-leveling program will assign the incoming User Data to a physical location unrelated to the physical location in which User Data of the same logical address had previously been stored. Old data associated with a particular logical address is not immediately overwritten by incoming data of the same logical address. The old data is simply obsoleted, and the incoming data is written into the next available Physical Data Block, that is, the next addressable Physical Data Block that is free and non-defective. As a result, t
Bragdon Reginald G.
Haverstock & Owens LLP
Lexar Media, Inc.
Vital Pierre M.
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