Flash memory and program verify method for flash memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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C365S185080, C365S185220

Reexamination Certificate

active

11116440

ABSTRACT:
In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuit3writes a fail value to a neighbor cell buffer5when all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer5. The control circuit3verifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.

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patent: WO 99/07000 (1999-02-01), None

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