Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Patent
1997-12-24
1999-10-12
Bragdon, Reginald G.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
711103, 711156, 711203, 39518501, G06F 1202
Patent
active
059667206
ABSTRACT:
A flash memory control apparatus and method which enables updating of data at high speed. The flash memory control apparatus includes a flash memory having a memory region which is divided into a plurality of sectors each including a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data; and a control device, coupled to the flash memory, for making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. The flash memory control method includes the steps of: (a) dividing a memory region of a flash memory into a plurality of sector; and (b) making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. Each of the sectors includes a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data
REFERENCES:
patent: 3685020 (1972-08-01), Meade
patent: 4758982 (1988-07-01), Price
patent: 4780815 (1988-10-01), Shiota
patent: 5072422 (1991-12-01), Rachels
patent: 5152338 (1992-10-01), Mehrotra
patent: 5297148 (1994-03-01), Harari et al.
patent: 5303198 (1994-04-01), Adachi et al.
patent: 5341330 (1994-08-01), Wells et al.
patent: 5353256 (1994-10-01), Fandrich et al.
patent: 5437020 (1995-07-01), Wells et al.
patent: 5463751 (1995-10-01), Yonezawa et al.
patent: 5479633 (1995-12-01), Wells et al.
patent: 5479638 (1995-12-01), Assar et al.
patent: 5485595 (1996-01-01), Assar et al.
patent: 5630093 (1997-05-01), Holzhammer et al.
Preliminary Search Report for corresponding French Application, dated Nov. 25, 1994.
Itoh Hiroyuki
Matsui Noriyuki
Bragdon Reginald G.
Fujitsu Limited
LandOfFree
Flash memory accessed using only the logical address does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flash memory accessed using only the logical address, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory accessed using only the logical address will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-662616