Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-12-14
2003-07-29
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C710S059000, C710S266000, C365S185290, C365S185330, C365S218000, C365S189070, C713S322000, C713S601000, C711S166000
Reexamination Certificate
active
06601131
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer with a built in flash memory.
2. Description of Related Art
Recently, flash memories have rapidly come onto the market. This is because, unlike EPROM (Erasable Programmable Read-Only Memory) requiring ultraviolet light for erasing, erasure as well as writing of data can be easily achieved electrically with flash memories, and hence the once written program and data (data and the like) can be easily updated. Thus, the microcomputer with a built-in flash memory using the flash memory in place of a mask ROM or EPROM for storing programs or data has also been rapidly extending its markets.
Just as a single chip flash memory not installed into a microcomputer, the flash memory installed in the microcomputer with a built-in flash memory can be written (programmed) and erased using a flash memory writer. While they are mounted on (soldered, connected to) a circuit board, however, the flash memory in the microcomputer with a built-in flash memory or the single chip flash memory cannot be connected to the flash writer, and hence cannot be written or erased by the flash writer. Thus, a microcomputer with a built-in flash memory with a CPU rewritable function is conceived which carries out writing and erasing by transferring data or the like to the flash memory using the CPU of the microcomputer with a built-in flash memory.
In other words, to solve the foregoing problem, a microcomputer with a built-in flash memory with a CPU rewritable function is proposed which can achieve writing and erasing of the flash memory installed in the microcomputer using the embedded CPU even after mounted on a circuit board.
FIG. 8
is a block diagram showing a configuration of a conventional microcomputer with a built-in flash memory with a CPU rewritable function. In this figure, the reference numeral
1
designates a microcomputer,
2
designates an internal bus,
3
designates a CPU with a BIU (Bus-Interface Unit) incorporating an instruction queue buffer
4
designates a flash memory,
5
designates a flash controller,
6
designates a RAM,
7
designates an input/output terminal,
8
designates a clock generator,
9
designates a monitor timer,
10
designates an interrupt controller,
11
designates an external bus,
12
designates a personal computer (called PC from now on),
13
designates an interface (I/F) and
14
designates an oscillator.
FIG. 7
is a block diagram showing an internal configuration of a flash controller
5
of the conventional and of the present invention microcomputer with a built-in flash memory. In this figure, the reference numeral
30
designates a flash writing/erasing executer,
31
designates a flash command register,
32
designates a flash control register, and
32
a
designates a busy bit in the flash control register
32
.
Next, the operation of the conventional microcomputer will be described.
The monitor timer
9
down-counts the clock signal CLK
2
the clock generator
8
generates from the oscillation signal supplied from the oscillator
14
, and supplies its underflow signal S
1
to the interrupt controller
10
. Receiving the underflow signal S
1
, the interrupt controller
10
issues an interrupt request to the CPU
3
by supplying it with a monitor timer interrupt signal S
2
. The CPU
3
sets a predetermined value to the monitor timer
9
at every fixed time interval using a setting signal S
3
so that if the CPU
3
runs away and the monitor timer
9
is not set within the predetermined time period, the monitor timer
9
underflows and generates the monitor timer interrupt signal S
2
. Detecting the monitor timer interrupt signal S
2
, the CPU
3
recognizes its own runaway, and returns to its normal operation by executing the corresponding interrupt service routine.
Next, data writing and erasing of the flash memory
4
using the CPU
3
will be described.
It is assumed here that the data to be written is supplied from the PC
12
to the interface
13
, and that a program for carrying out the following operations is stored in a particular area of the flash memory
4
or in the RAM
6
, and the CPU
3
operates in accordance with the program. When the flash memory
4
stores the program, it must transfer the program to the RAM
6
in advance to execute the program on the RAM
6
. This is because the CPU
3
cannot fetch operation code from the flash memory
4
during writing/erasing of the flash memory
4
. The transfer of the program to the RAM
6
can present such problems as occupying a memory area on the RAM
6
, taking time for transferring the program, and consuming time to develop software.
In the write operation, the CPU
3
writes “1” into a CPU rewriting mode designating bit in the flash control register
32
in the flash controller
5
, first. In response to this, the flash control register
32
supplies the CPU rewriting mode designating signal S
4
to the flash writing/erasing executer
30
. The flash writing/erasing executer
30
waits for a command to be written in the flash command register
31
. Subsequently, when the CPU
3
writes a write command in the flash command register
31
, the flash writing/erasing executer
30
decodes the command, and starts a sequence of writing into the flash memory
4
. Then, the CPU
3
reads the data to be written through the interface
13
, and writes the data into the flash memory
4
. Thus, the flash writing/erasing executer
30
executes actual writing of the data to the flash memory
4
in a prescribed sequence.
In the course of writing to the flash memory
4
, the flash writing/erasing executer
30
generates a clock signal and counts it to execute the write process step by step at prescribed time independently of the operation of the CPU
3
. Since the CPU
3
can read the write busy signal S
5
indicating that the write process is being executed through the busy bit
32
a
in the flash control register
32
, the CPU
3
continues reading the busy bit
32
a
throughout the course, and waits for the busy signal S
5
to be disabled, that is, waits for the end of the write operation.
Assuring that the busy signal S
5
is disabled, the CPU
3
verifies whether the data is written into the flash memory
4
correctly by a well known, method. When the data is written correctly, the CPU
3
carries out the next data write in the same manner as described above.
As for the erasure of the flash memory
4
, the CPU
3
can execute it by setting a CPU rewriting mode into the flash control register
32
in the flash controller
5
, and then by writing an erasing command into the flash command register
31
.
Decoding the erasing command, the flash writing/erasing executer
30
executes the erasure of the flash memory
4
in accordance with a prescribed sequence. In the course of erasing the flash memory
4
, since the busy signal S
5
is enabled, the CPU
3
continues reading the busy bit
32
a
in the flash control register
32
(polling).
Since the writing and erasing time period is much longer than a common operation period of the PC, the monitor timer
9
, which is provided for detecting a runaway of the CPU
3
, can underflow, thereby causing an undesired monitor timer interrupt. To prevent the undesired monitor timer interrupt, the CPU
3
must generate the setting signal S
3
within a predetermined period to reset the value of the monitor timer
9
.
As described above, in the microcomputer with a built-in flash memory, the CPU
3
must execute the polling continuously during the writing/erasing of the flash memory
4
to detect its end. In addition, since the monitor timer
9
continues its operation during the rewriting/erasing of the flash memory
4
, an instruction for resetting the value of the monitor timer
9
must be inserted in many places of the program to prevent the underflow of the value of the monitor timer
9
.
To solve such a problem, Japanese patent application laid-open No. 10-177563/1998, for example, proposes a new microcomputer with a built-in flash memory. This microcomputer with a
Hongo Katsunobu
Koura Masato
Sezaki Toshihiro
Burns Doane , Swecker, Mathis LLP
Peikari B. James
LandOfFree
Flash memory access control via clock and interrupt management does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flash memory access control via clock and interrupt management, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory access control via clock and interrupt management will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3047505