Flash memory

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S316000

Reexamination Certificate

active

11161994

ABSTRACT:
A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings. The conductive spacers are patterned to form a plurality of floating gates. A plurality of buried doped regions is formed in the substrate under the bottom surface of the openings. An inter-gate dielectric layer is formed over the substrate. A plurality of control gates is formed over the substrate to fill the openings. The mask layer is removed to form a plurality of memory units. A plurality of source regions and drain regions are formed in the substrate beside the memory units.

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patent: 6081449 (2000-06-01), Sekariapuram et al.
patent: 6091102 (2000-07-01), Sekariapuram et al.
patent: 6093945 (2000-07-01), Yang
patent: 6724029 (2004-04-01), Hsu et al.
patent: 6875660 (2005-04-01), Hung et al.
patent: 2002/0072170 (2002-06-01), Lam
patent: 2002/0109179 (2002-08-01), Johnson et al.
patent: 2005/0280073 (2005-12-01), Huang et al.
patent: 2005/0282337 (2005-12-01), Shyu et al.
patent: 2006/0102948 (2006-05-01), Chang et al.
patent: 2006/0157773 (2006-07-01), Yu et al.

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