Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-04-25
2002-05-21
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S322000
Reexamination Certificate
active
06392267
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to nonvolatile memory integrated circuits and more particularly to flash EPROM arrays.
BACKGROUND OF THE INVENTION
Nonvolatile memory integrated circuits typically include memory cells arranged in one or more arrays. A common type of nonvolatile memory integrated circuit is an electrically programmable read-only-memory (EPROM). The memory cells of EPROMs commonly utilize floating gate structures which can store charge, and thereby indicate a certain logic state. Electrically programmable ROMs include UVPROMs in which the cells are programmed by hot electron injection or tunneling, and erased by the application of ultra-violet light; EE PROMS in which the cells are programmed and erased by tunneling; and “flash” EPROMs in which the cells are programmed by hot electron injection or tunneling, and groups of cells are simultaneously erased by tunneling.
The reading, programming, and erasing of EPROM memory cells requires the application of certain voltages to each cell. For example, in U.S. Pat. No. 4,698,787 issued to Mukherjee et al. on Oct. 6, 1987, a flash EPROM is disclosed having one transistor (“1-T”) cells where the cells are read by grounding the sources of the cells, applying a positive voltage to the gate, and sensing the resulting potential at the drain. The cells of Mukherjee et al. are programmed by grounding the sources of the cells, and applying a positive gate and drain voltage. Erasure of the cells of Mukherjee et al. is accomplished by floating the drains of a group of cells and placing the sources of the cells in the group at a higher potential than their respective gates. In Mukherjee et al., because the memory cells are flash erased, there is no need to differentiate source connections. As a result, a common source diffusion is utilized. The use of a common source diffusion leads to a compact array design.
The use of a common source diffusion can give rise to a number of limitations in the implementation of a flash EPROM. For example, when a selected cell coupled to the common source diffusion is programmed, the inherent resistance of the diffused region can result in the poor programming of selected cells, due to the source potential generated by the programming current. Accordingly, the size of common source regions in flash EPROM are limited to minimize common source resistance. In addition, in the case where the erase voltage between the control gate and the source is accomplished by placing the sources at a higher potential with respect to the gate and also with respect to the substrate, substrate junction leakage can result. Such junction leakage can result in source current which can affect erase speed due to source voltage drop. Alternately, a process requiring a higher source breakdown voltage may be needed. For example, Mukherjee et al. employs a double diffused source region to increase the source breakdown voltage. U.S. Pat. No. 4,742,492 issued to Smayling et al. on May, 3 1988, and U.S. Pat. No. 5,077,691 issued Haddad et al. on Dec. 31, 1991 disclose the use of a negative word line erase potential in conjunction with a relatively low positive common source voltage to limit the substrate-to-source potential during erase.
Yet another issue raised by diffused common source regions is the array area required for such approaches. Referring now to
FIG. 1
a
, a portion of a prior art flash EPROM array is set forth in a top plan view. The portion of the array set forth includes three rows of cells, shown as items
1
a
-
1
c
. Each row of cells includes memory cells
2
a
-
2
c
and
3
a
-
3
c
. Each memory cell includes a floating gate (indicated by diagonal hatching), a control gate formed over the floating gates of each row (indicated by horizontal hatching), and source and drain regions separated by channel regions. The drain regions are designated as
4
a
-
4
c
and
5
a
-
5
c
. Bit line contacts
6
a
-
6
d
are provided for coupling the drain regions of the memory cells to bit lines (not shown). Each bit line contact
6
a
-
6
d
is shared by two memory cells from different rows. Memory cells
2
a
,
2
b
,
3
a
and
3
b
share a common source region
7
that extends in the row direction. In the arrangement of
FIG. 1
a
, the common source region
7
is formed as part of an active region separated by isolation regions. The active regions are created prior to the formation of the control gate of the memory cells
2
a
-
2
c
and
3
a
-
3
c
. As a result, in order to ensure that misalignments inherent in the fabrication process will not create memory cells having control gates that overlap the source region, the control gates must be formed at a minimum distance away from source region. The minimal spacing requirement results in larger arrays.
In the previous art, all the source contacts are tied together because of the need to minimize source resistance. Erase voltages are typically supplied to the common sources by a “strapping” interconnect, such as metal. This type of arrangement does not allow smaller portions of the array to be erased at will, and results in arrays having minimum, predetermined erasable portions (“granularity”).
FIG. 1
b
sets forth a prior art approach to eliminating the source spacing requirement by fabricating a “self-aligned” common source region.
FIG. 1
b
has many of the same features of
FIG. 1
a
, and so like elements will be referred to by the same reference character. The self-aligned common source of
FIG. 1
b
differs from the arrangement of
FIG. 1
a
in that the source regions include active area source regions
7
a
and etched source regions
7
b
. As in the case of the
FIG. 1
a
, architecture the active area source regions
7
a
are formed prior to the control gates of the memory array. Unlike
FIG. 1
a
, the etched source regions
7
b
are created after the floating gate and control gate are formed, by etching through field oxide regions and implanting dopants into the exposed etched source region to increase the conductivity of the source. While allowing memory cells to be placed closer to the source region, the self-aligned common source region approach, such as that set forth in
FIG. 1
b
, includes some drawbacks. Despite the implantation step, the resulting resistance of the common source introduces a limit to the number of memory cells that may be coupled to the common source before periodic contacts using a low resistance interconnect such as metal must be made to the source region. A periodic contact
8
for the common source region is set forth in the
FIG. 1
b
arrangement. As shown in the figure, the periodic contact requires its own active area and so disturbs the pitch of the memory cells, reducing the compactness of the resulting array. Another issue raised by the self-aligned common source region such as that set forth in
FIG. 1
b
, is illustrated by
FIG. 1
c
.
FIG. 1
c
is a side cross sectional view taken along line c—c in
FIG. 1
b
.
FIG. 1
c
sets forth portions of memory cells
3
a
and
3
b
, which both include control gates (word lines)
9
a
and
9
b
, and floating gates
10
a
and
10
b
. The control gates and floating gates are protected on their side surfaces by a source sidewall spacers
11
and drain sidewall spacers
12
. The memory cells (
3
a
and
3
b
) along line c—c sit on a insulation area formed from field oxide
13
. In order to form the etched source region
7
b
, a trench
14
must be etched through the field oxide
13
in a self-aligned source etch step. The action of etching through the field oxide
13
results in some etching of the source sidewall spacers
11
, which can lead to charge leakage in the memory cell, impacting the reliability of the memory device.
It would be desirable to arrive at an EPROM array without the drawbacks of prior art approaches.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a non-volatile memory cell array having a reduced area by eliminating the need of source “strapping”.
It is another object of the present invention to provide a non-volatile memor
Reddy Chitranjan N.
Shrivastava Ritu
Alliance Semiconductor Corporation
Crane Sara
Stallman & Pollock LLP
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