Flash electrically erasable and programmable ROM

Static information storage and retrieval – Read/write circuit – Erase

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Details

365185, 36518911, 365900, G11C 1140

Patent

active

053094026

ABSTRACT:
A flash EEPROM with sector erasure, carries out the erasure by applying a negative voltage to a selected word line through an N-channel MOS transistor. P-channel MOS transistors are respectively inserted between row decoder level shifters and each of their respective word lines to which they are respectively connected. The turning-on and -off of the respective word lines and first level shifters is controlled by the turning-on and -off of the associated P-channel MOS transistor. An erase voltage is applied to one end of the source/drain path of the respective N-channel MOS transistor of the selected cord line, the other end to the respective word lines. The turning-on and -off of the N-channel MOS transistor is synchronized with the turning-on and -off of the P-channel MOS transistor connected to the same word line. The P-channel MOS transistor is formed on an N well biased to, for example, 5 V and the N-channel MOS transistor is formed on a P well biased to, for example, the erase voltage. The P well is formed on the surface of the N well.

REFERENCES:
patent: 5022000 (1991-06-01), Terasawa et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5084843 (1992-01-01), Mitsuishi et al.
Virgil Niles Kynett et al, "An In-System Reprogrammable 32K.times.8 CMOS Flash Memory", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1157-1163.
S. Aritome et a, "A Reliable Bi-Polarity Write/Erase Technology In Flash EEPROMs", IEDM Technical Digest, 1990, pp. 111-114.
N. Ajika et al, "A 5 Volt Only 16M Bit Flash EEPROM Cell With a Simple Stacked Gate Structure", IEDM Digest, 1990, pp. 115-118.

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