Flash EEPROM with function bit by bit erasing

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S288000, C257S300000, C257S239000, C257S261000, C438S201000, C438S211000, C438S257000, C711S103000

Reexamination Certificate

active

06933555

ABSTRACT:
A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in addition to page erasing, of a plurality of cells of two or more is disclosed through the application of a positive voltage forced onto the control gate of the unselected cell. Thus, by providing the bit-by-bit erasing flexibility, the bit alterability is enhanced. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. The programming, that is, writing of the plurality of N+1 bits is accomplished also bit by bit where the programmed bits are selected by word line, bit line and control gate. The read operation is similar to the write operation. Thus, it is disclosed here that a plurality of N+1 bits or cells, where N is any integer, can be formed between two bit lines and along the same word line and also be programmed with enhanced bit alterability.

REFERENCES:
patent: 5278439 (1994-01-01), Ma et al.
patent: 5677872 (1997-10-01), Samachisa et al.
patent: 5712179 (1998-01-01), Yuan
patent: 6028336 (2000-02-01), Yuan
patent: 6151248 (2000-11-01), Harari et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6723604 (2004-04-01), Yuan et al.
Y. Ma et al., “A Dual-bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories,” IEDM 94-57, 1994 IEEE, pp. 3.5.1 to 3.5.4.

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