Flash EEPROM unit cell and memory array architecture...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S314000, C257S316000, C257S320000, C257S321000, C257S322000, C257S326000

Reexamination Certificate

active

06940122

ABSTRACT:
A high-density flash EEPROM (Electrically Erasable Programmable Read Only Memory) unit cell and a memory array architecture including the same are disclosed. The flash EEPROM unit cell comprises a substrate on which field oxide layers are formed for isolating unit cells, a floating gate dielectric layer formed between the adjacent field oxide layers, wherein the floating gate dielectric layer includes a first dielectric layer and a second dielectric layer which are connected in parallel between a source and a drain formed on the substrate, and the thickness of the first dielectric layer is thicker than the second dielectric layer, a floating gate formed on the floating gate dielectric layer, a control gate dielectric layer formed on the floating gate; and a control gate formed on the control gate dielectric layer.

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patent: 6642105 (2003-11-01), Kim et al.
patent: 6759706 (2004-07-01), Kobayashi
patent: 6815283 (2004-11-01), Lee

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