Flash EEPROM memory with reduced column leakage current

Details Flash EEPROM memory with reduced column leakage current Flash EEPROM memory with reduced column leakage current

1996-07-22

1997-07-29

Heinz, A. J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257314, 257321, 3651853, 3651851, H01L 29788, H01L 2976, G11C 1134

Patent

active

056524471

ABSTRACT:
A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant step suitably provides an enhanced doping profile in the tunneling region, which increases the rate at which F-N tunneling occurs to erase the cells, and which increases the uniformity of F-N tunneling rates among memory cells within the array. A thermal cycle drives the intermediate n+ implant deeper into the tunneling region. Alternatively, an n+ implant may be performed at a relatively large angle with respect to the semiconductor substrate, which improves the doping concentration in the tunneling region of the source.

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patent: 5317179 (1994-05-01), Chen et al.
patent: 5335198 (1994-08-01), Van Buskirk et al.
patent: 5446298 (1995-08-01), Kojima
patent: 5557566 (1996-09-01), Ochii
patent: 5569946 (1996-10-01), Hong
patent: 5587947 (1996-12-01), Chang et al.

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