Flash EEPROM Memory system for low voltage operation and method

Static information storage and retrieval – Floating gate

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36518529, 365218, G11C 700

Patent

active

056027753

ABSTRACT:
A flash memory system utilizing low threshold voltage cells so as to provide adequate cell current during read operations even with at low power supply voltages. The cells are arranged into an array of rows and columns, with the source regions of all of the cells connected to a common source line, the drain regions of the cells in one of the columns connected to a common bit line and the control gates of the cells in one of the rows connected to a common word line. In program operations, voltages are applied to the cells so that the program current flows from the cell bit line to the common source line. This results in electrons being injected from the drain toward the floating gate and the floating gate thereby altering the threshold voltage of the cell. In read operation, voltages are applied so that current flow is in the opposite direction, namely from the source line to the bit line. The read current is then sensed at the source line by way of a sense amplifier and associated circuitry. This arrangement minimizes undesirable leakage currents during read operations notwithstanding the use of low threshold voltage memory cells.

REFERENCES:
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5280446 (1994-01-01), Ma et al.
patent: 5313432 (1994-05-01), Lin et al.
patent: 5341329 (1994-08-01), Takebuchi

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